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74VHCT574A_04 PDF预览

74VHCT574A_04

更新时间: 2024-11-21 05:05:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器输出元件
页数 文件大小 规格书
13页 276K
描述
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING

74VHCT574A_04 数据手册

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74VHCT574A  
OCTAL D-TYPE FLIP FLOP  
WITH 3 STATE OUTPUTS NON INVERTING  
HIGH SPEED:  
= 180 MHz (TYP.) at V = 5V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 4 µA (MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS:  
= 2V (MIN.), V = 0.8V (MAX)  
V
IH  
IL  
SOP  
TSSOP  
T & R  
POWER DOWN PROTECTION ON INPUTS  
& OUTPUTS  
Table 1: Order Codes  
PACKAGE  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8 mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
SOP  
74VHCT574AMTR  
74VHCT574ATTR  
t
t
PLH  
PHL  
TSSOP  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
V
CC  
When the (OE) input is low, the 8 outputs will be in  
a normal logic state (high or low logic level) and  
when (OE) is high, the outputs will be in a high  
impedance state.  
The Output control does not affect the internal  
operation of flip flop; that is, the old data can be  
retained or the new data can be entered even  
while the outputs are off.  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
inputs with no regard to the supply voltage. This  
device can be used to interface 5V to 3V since all  
inputs are equipped with TTL threshold.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 574  
IMPROVED LATCH-UP IMMUNITY  
LOW NOISE: V  
= 0.9V (MAX.)  
OLP  
DESCRIPTION  
The 74VHCT574A is an advanced high-speed  
CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE  
OUTPUTS NON INVERTING fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS technology.  
These 8 bit D-Type flip-flop is controlled by a clock  
input (CK) and an output enable input (OE).  
On the positive transition of the clock, the Q  
outputs will be set to the logic states that were  
setup at the D inputs.  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/13  
December 2004  

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