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74LVT574D,112 PDF预览

74LVT574D,112

更新时间: 2024-11-26 14:40:15
品牌 Logo 应用领域
恩智浦 - NXP 驱动信息通信管理光电二极管逻辑集成电路触发器
页数 文件大小 规格书
17页 150K
描述
74LVT(H)574 - 3.3 V octal D-type flip-flop; 3-state SOP 20-Pin

74LVT574D,112 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOP包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.25
其他特性:BROADSIDE VERSION OF 374系列:LVT
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:150000000 Hz
最大I(ol):0.064 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3 V最大电源电流(ICC):12 mA
Prop。Delay @ Nom-Sup:5.9 ns传播延迟(tpd):6.6 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:7.5 mm
Base Number Matches:1

74LVT574D,112 数据手册

 浏览型号74LVT574D,112的Datasheet PDF文件第2页浏览型号74LVT574D,112的Datasheet PDF文件第3页浏览型号74LVT574D,112的Datasheet PDF文件第4页浏览型号74LVT574D,112的Datasheet PDF文件第5页浏览型号74LVT574D,112的Datasheet PDF文件第6页浏览型号74LVT574D,112的Datasheet PDF文件第7页 
74LVT574; 74LVTH574  
3.3 V octal D-type flip-flop; 3-state  
Rev. 7 — 22 November 2011  
Product data sheet  
1. General description  
The 74LVT574; 74LVTH574 is a high-performance product designed for VCC operation at  
3.3 V.  
This device is an 8-bit, edge triggered register coupled to eight 3-state output buffers. The  
two sections of the device are controlled independently by the clock (pin CP) and output  
enable (pin OE) control gates. The state of each Dn input (one setup time before the  
LOW-to-HIGH clock transition) is transferred to the corresponding flip-flops Qn output.  
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS  
memories, or MOS microprocessors.  
The active LOW output enable (pin OE) controls all eight 3-state buffers independent of  
the clock operation.  
When pin OE is LOW, the stored data appears at the outputs. When pin OE is HIGH, the  
outputs are in the high-impedance OFF-state, which means they will neither drive nor load  
the bus.  
2. Features and benefits  
Inputs and outputs arranged for easy interfacing to microprocessors  
3-state outputs for bus interfacing  
Common output enable control  
TTL input and output switching levels  
Input and output interface capability to systems at 5 V supply  
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs  
Live insertion and extraction permitted  
No bus current loading when output is tied to 5 V bus  
Power-up reset  
Power-up 3-state  
Latch-up protection  
JESD78 class II exceeds 500 mA  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from 40 C to +85 C  
 
 

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