Datasheet > 74LVQ00_04

74LVQ00_04

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		输入元件
页数	文件大小	规格书
11页	288K
描述
LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE

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数据手册

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74LVQ00_04 数据手册

74LVQ00

LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE

■

HIGH SPEED:

= 5.5ns (TYP.) at V = 3.3 V

■

COMPATIBLE WITH TTL OUTPUTS

LOW POWER DISSIPATION:

= 2µA (MAX.) at T =25°C

■

LOW NOISE:

= 0.3V (TYP.) at V = 3.3V

75Ω TRANSMISSION LINE DRIVING

CAPABILITY

SOP

TSSOP

OLP

Table 1: Order Codes

PACKAGE

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 12mA (MIN) at V = 3.0V

T & R

■

PCI BUS LEVELS GUARANTEED AT 24 mA

BALANCED PROPAGATION DELAYS:

SOP

74LVQ00MTR

74LVQ00TTR

TSSOP

PLH

PHL

■

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 3.6V (1.2V Data Retention)

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 00

technology. It is ideal for low power and low noise

3.3V applications.

The internal circuit is composed of 3 stages

including buffer output, which enables high noise

immunity and stable output.

IMPROVED LATCH-UP IMMUNITY

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

DESCRIPTION

The 74LVQ00 is a low voltage CMOS QUAD

2-INPUT NAND GATE fabricated with sub-micron

silicon gate and double-layer metal wiring C MOS

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 5

1/11

July 2004

12 3 4 5 6 7...11

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