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74LVQ00T PDF预览

74LVQ00T

更新时间: 2024-11-08 22:15:31
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
8页 59K
描述
QUAD 2-INPUT NAND GATE

74LVQ00T 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP14,.25
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.78
Is Samacsys:N系列:LVQ
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.024 A
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:9 ns传播延迟(tpd):14 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.2 mm子类别:Gates
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

74LVQ00T 数据手册

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74LVQ00  
QUAD 2-INPUT NAND GATE  
HIGH SPEED:tPD =5.5ns (TYP.) atVCC = 3.3V  
COMPATIBLEWITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
o
µ
I
CC =2 A (MAX.) at TA =25 C  
LOWNOISE:  
M
T
VOLP =0.3 V (TYP.)at VCC = 3.3V  
(Micro Package)  
(TSSOPPackage)  
75 TRANSMISSIONLINEDRIVING  
ORDER CODES :  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 12 mA (MIN)  
74LVQ00M  
74LVQ00T  
technology.It is ideal for low power and low noise  
3.3V applications.  
The internal circuit is composed of 3 stages  
including buffer output, which enables high noise  
immunity and stable output.  
It has better speed performance at 3.3V than 5V  
LS-TTL family combined with the true CMOS low  
power consumption.  
PCI BUSLEVELSGUARANTEED AT 24mA  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 3.6V(1.2VDataRetention)  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES00  
IMPROVED LATCH-UP IMMUNITY  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The LVQ00 is a low voltage CMOS QUAD  
2-INPUT NAND GATE fabricated with sub-micron  
silicon gate and double-layermetal wiring C2MOS  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
February 1999  

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