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74LVQ00SJ PDF预览

74LVQ00SJ

更新时间: 2024-11-22 22:15:31
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 56K
描述
Low Voltage Quad 2-Input NAND Gate

74LVQ00SJ 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.3
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.23
Is Samacsys:N系列:LVQ
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:10.2 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.012 A
湿度敏感等级:1功能数量:4
输入次数:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TUBE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:10 ns传播延迟(tpd):14 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2.1 mm子类别:Gates
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

74LVQ00SJ 数据手册

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February 1992  
Revised April 2001  
74LVQ00  
Low Voltage Quad 2-Input NAND Gate  
General Description  
The LVQ00 contains four 2-input NAND gates.  
Features  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Guaranteed pin-to-pin skew AC performance  
Guaranteed incident wave switching into 75  
Ordering Code:  
Order Number  
74LVQ00SC  
74LVQ00SJ  
Package Number  
M14A  
Package Description  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M14D  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
An, Bn  
Description  
Inputs  
Outputs  
On  
© 2001 Fairchild Semiconductor Corporation  
DS011341  
www.fairchildsemi.com  

74LVQ00SJ 替代型号

型号 品牌 替代类型 描述 数据表
74LVQ00SC FAIRCHILD

完全替代

Low Voltage Quad 2-Input NAND Gate
74LVQ00SCX FAIRCHILD

类似代替

Low Voltage Quad 2-Input NAND Gate

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