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74LVC2244 PDF预览

74LVC2244

更新时间: 2024-01-04 11:24:40
品牌 Logo 应用领域
恩智浦 - NXP 驱动器
页数 文件大小 规格书
16页 88K
描述
Octal buffer/line driver with 30 ohm series termination resistors; 5 V input/output tolerant; 3-state

74LVC2244 技术参数

生命周期:Obsolete包装说明:TSSOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.11系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G20长度:6.5 mm
逻辑集成电路类型:BUS DRIVER位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

74LVC2244 数据手册

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Philips Semiconductors  
Product specification  
Octal buffer/line driver with 30 series termination  
resistors; 5 V input/output tolerant; 3-state  
74LVC2244A  
FEATURES  
DESCRIPTION  
5 V tolerant inputs/outputs for interfacing with 5 V logic  
Wide supply voltage range of 1.2 to 3.6 V  
CMOS low power consumption  
The 74LVC2244A is a high-performance, low-power,  
low-voltage, Si-gate CMOS device, superior to most  
advanced CMOS compatible TTL families.  
Inputs can be driven from either 3.3 or 5 V devices. In  
3-state operation, outputs can handle 5 V. These features  
allow the use of these devices as translators in a mixed  
3.3/5 V environment.  
Direct interface with TTL levels  
Integrated 30 termination resistors.  
The 74LVC2244A is an octal non-inverting buffer/line  
driver with 3-state outputs. The 3-state outputs are  
controlled by the output enable inputs 1OE and 2OE. A  
HIGH on nOE causes the outputs to assume a  
high-impedance OFF-state. Schmitt-trigger action at all  
inputs makes the circuit highly tolerant for slower input rise  
and fall times. The 74LVC2244A is designed with 30 Ω  
series termination resistors in both HIGH and LOW output  
stages to reduce line noise.  
QUICK REFERENCE DATA  
Ground = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.  
SYMBOL  
PARAMETER  
propagation delay 1An to 1Yn; 2An to 2Yn  
input capacitance  
CONDITIONS  
TYPICAL  
4.0  
UNIT  
t
PHL/tPLH  
CL = 50 pF; VCC = 3.3 V  
ns  
pF  
pF  
CI  
5.0  
25  
CPD  
power dissipation capacitance per buffer  
VI = GND to VCC; note 1  
Note  
1. CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in Volts;  
Σ(CL × VCC2 × fo) = sum of the outputs.  
1999 Sep 30  
2

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