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74LV161284DGGRE4 PDF预览

74LV161284DGGRE4

更新时间: 2024-01-11 08:41:38
品牌 Logo 应用领域
德州仪器 - TI 驱动器接口集成电路光电二极管
页数 文件大小 规格书
11页 185K
描述
19-BIT BUS INTERFACE

74LV161284DGGRE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:GREEN, PLASTIC, TSSOP-48针数:48
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.75
Is Samacsys:N差分输出:NO
驱动器位数:13输入特性:SCHMITT TRIGGER
接口集成电路类型:LINE TRANSCEIVER接口标准:IEEE 1284
JESD-30 代码:R-PDSO-G48JESD-609代码:e4
长度:12.5 mm湿度敏感等级:1
功能数量:13端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
最大接收延迟:30 ns接收器位数:17
座面最大高度:1.2 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED最大传输延迟:30 ns
宽度:6.1 mmBase Number Matches:1

74LV161284DGGRE4 数据手册

 浏览型号74LV161284DGGRE4的Datasheet PDF文件第3页浏览型号74LV161284DGGRE4的Datasheet PDF文件第4页浏览型号74LV161284DGGRE4的Datasheet PDF文件第5页浏览型号74LV161284DGGRE4的Datasheet PDF文件第7页浏览型号74LV161284DGGRE4的Datasheet PDF文件第8页浏览型号74LV161284DGGRE4的Datasheet PDF文件第9页 
SN74LV161284  
19-BIT BUS INTERFACE  
SCLS426C OCTOBER 1998 REVISED NOVEMBER 2002  
PARAMETER MEASUREMENT INFORMATION  
V
CC  
t
w
V
CC  
Input  
(see Note B)  
C
= 50 pF  
V
CC  
/2  
V
CC  
/2  
L
62 Ω  
(see Note A)  
0 V  
t
t
PHL  
PLH  
TP1  
Sink Load  
From  
B or Y Output  
Under Test  
V
OH  
1.4 V  
t
PHL  
Output  
(see Note B)  
V
OL  
+ 1.4 V  
V
OH  
t
PLH  
Source Load  
V
OL  
VOLTAGE WAVEFORMS MEASURED AT TP1  
PROPAGATION DELAY TIMES (A to B)  
C
= 50 pF  
L
62 Ω  
(see Note A)  
SLEW RATE A-TO-B OR A-TO-Y LOAD (Totem Pole)  
V
CC  
V
CC  
Input  
(see Note C)  
V
CC  
/2  
V
CC  
/2  
0 V  
TP1  
500 Ω  
V
OH  
OL  
Output  
(see Note C)  
2 V  
0.8 V  
2 V  
0.8 V  
From  
B or Y Output  
V
C
= 50 pF  
L
(see Note A)  
t
t
f
r
VOLTAGE WAVEFORMS MEASURED AT TP1, B SIDE  
A-TO-B LOAD OR A-TO-Y LOAD (Open Drain)  
NOTES: A.  
C includes probe and jig capacitance.  
L
B. Input rise and fall times are 3 ns, 150 ns < pulse duration < 10 µs for both low-to-high and high-to-low transitions.  
Slew rate is measured between 0.4 V and 1.9 V for the rising edge and between 95% V  
C. Input rise and fall times are 3 ns. Rise and fall times (open drain) < 120 ns.  
D. The outputs are measured one at a time with one transition per measurement.  
and 50% V for the falling edge.  
CC  
CC  
Figure 1. Load Circuits and Voltage Waveforms  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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