Datasheet > 74LS175

74LS175

更新时间： 2024-02-15 11:14:19

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器
页数	文件大小	规格书
5页	174K
描述
QUAD D FLIP-FLOP

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技术参数
数据手册

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74LS175 技术参数

生命周期：	Obsolete	包装说明：	SOP, SOP16,.25
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.49	JESD-30 代码：	R-PDSO-G16
逻辑集成电路类型：	D FLIP-FLOP	功能数量：	4
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	5 V	认证状态：	Not Qualified
子类别：	FF/Latches	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	TTL
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
触发器类型：	POSITIVE EDGE	Base Number Matches：	1

74LS175 数据手册

SN54/74LS175

QUAD D FLIP-FLOP

The LSTTL/MSI SN54/74LS175 is a high speed Quad D Flip-Flop. The

device is useful for general flip-flop requirements where clock and clear inputs

are common. The information on the D inputs is stored during the LOW to

HIGH clock transition. Both true and complemented outputs of each flip-flop

are provided. A Master Reset input resets all flip-flops, independent of the

Clock or D inputs, when LOW.

QUAD D FLIP-FLOP

The LS175 is fabricated with the Schottky barrier diode process for high

speed and is completely compatible with all Motorola TTL families.

LOW POWER SCHOTTKY

• Edge-Triggered D-Type Inputs

• Buffered-Positive Edge-Triggered Clock

• Clock to Output Delays of 30 ns

• Asynchronous Common Reset

• True and Complement Output

• Input Clamp Diodes Limit High Speed Termination Effects

J SUFFIX

CERAMIC

CASE 620-09

CONNECTION DIAGRAM DIP (TOP VIEW)

NOTE:

N SUFFIX

PLASTIC

CASE 648-08

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

D SUFFIX

SOIC

CASE 751B-03

PIN NAMES

LOADING (Note a)

HIGH

LOW

D –D

Data Inputs

0.5 U.L.

10 U.L.

0.25 U.L.

5 (2.5) U.L.

Clock (Active HIGH Going Edge) Input

Master Reset (Active LOW) Input

True Outputs (Note b)

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

Q –Q

SN74LSXXXN Plastic

SN74LSXXXD SOIC

Q –Q

Complemented Outputs (Note b)

NOTES:

a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.

b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

b. Temperature Ranges.

LOGIC SYMBOL

LOGIC DIAGRAM

FAST AND LS TTL DATA

5-327

12 3 4 5

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