74LS175DCQM

更新时间： 2024-01-23 08:37:51

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
7页	76K
描述
D Flip-Flop, 4-Func, Positive Edge Triggered, TTL, CDIP16,

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技术参数
数据手册

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74LS175DCQM 技术参数

生命周期：	Obsolete	包装说明：	SOP, SOP16,.25
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.49	JESD-30 代码：	R-PDSO-G16
逻辑集成电路类型：	D FLIP-FLOP	功能数量：	4
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	5 V	认证状态：	Not Qualified
子类别：	FF/Latches	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	TTL
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
触发器类型：	POSITIVE EDGE	Base Number Matches：	1

74LS175DCQM 数据手册

August 1992

Revised April 2000

DM74LS174 • DM74LS175

Hex/Quad D-Type Flip-Flops with Clear

General Description

Features

These positive-edge-triggered flip-flops utilize TTL circuitry

to implement D-type flip-flop logic. All have a direct clear

input, and the quad (175) versions feature complementary

outputs from each flip-flop.

■ DM74LS174 contains six flip-flops with single-rail

outputs

■ DM74LS175 contains four flip-flops with double-rail

outputs

Information at the D inputs meeting the setup time require-

ments is transferred to the Q outputs on the positive-going

edge of the clock pulse. Clock triggering occurs at a partic-

ular voltage level and is not directly related to the transition

time of the positive-going pulse. When the clock input is at

either the HIGH or LOW level, the D input signal has no

effect at the output.

■ Buffered clock and direct clear inputs

■ Individual data input to each flip-flop

■ Applications include:

Buffer/storage registers

Shift registers

Pattern generators

■ Typical clock frequency 40 MHz

■ Typical power dissipation per flip-flop 14 mW

Ordering Code:

Order Number Package Number

Package Description

DM74LS174M

DM74LS174SJ

DM74LS174N

DM74LS175M

DM74LS175SJ

DM74LS175N

M16A

M16D

N16E

M16A

M16D

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

DM74LS174

DM74LS175

DS006404

www.fairchildsemi.com

12 3 4 5 6 7

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