Datasheet > 74LS175

74LS175

更新时间： 2024-02-01 16:11:35

品牌	Logo	应用领域
美国国家半导体 - NSC		触发器
页数	文件大小	规格书
8页	177K
描述
Hex/Quad D Flip-Flops with Clear

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技术参数
数据手册

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74LS175 技术参数

生命周期：	Obsolete	包装说明：	SOP, SOP16,.25
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.49	JESD-30 代码：	R-PDSO-G16
逻辑集成电路类型：	D FLIP-FLOP	功能数量：	4
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	5 V	认证状态：	Not Qualified
子类别：	FF/Latches	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	TTL
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
触发器类型：	POSITIVE EDGE	Base Number Matches：	1

74LS175 数据手册

June 1989

54LS174/DM54LS174/DM74LS174,

54LS175/DM54LS175/DM74LS175

Hex/Quad D Flip-Flops with Clear

General Description

Features

LS174 contains six flip-flops with single-rail outputs

These positive-edge-triggered flip-flops utilize TTL circuitry

to implement D-type flip-flop logic. All have a direct clear

input, and the quad (175) versions feature complementary

outputs from each flip-flop.

LS175 contains four flip-flops with double-rail outputs

Buffered clock and direct clear inputs

Individual data input to each flip-flop

Applications include:

Buffer/storage registers

Shift registers

Pattern generators

Information at the D inputs meeting the setup time require-

ments is transferred to the Q outputs on the positive-going

edge of the clock pulse. Clock triggering occurs at a particu-

lar voltage level and is not directly related to the transition

time of the positive-going pulse. When the clock input is at

either the high or low level, the D input signal has no effect

at the output.

Typical clock frequency 40 MHz

Typical power dissipation per flip-flop 14 mW

Alternate

Military/Aerospace

device

(54LS174,

54LS175) is available. Contact a National Semiconduc-

tor Sales Office/Distributor for specifications.

Connection Diagrams

Dual-In-Line Package

TL/F/6404–1

Order Number 54LS174DMQB, 54LS174FMQB,

54LS174LMQB, DM54LS174J,

TL/F/6404–2

Order Number 54LS175DMQB, 54LS175FMQB,

54LS175LMQB, DM54LS175J

DM54LS174W, DM74LS174M or DM74LS174N

See NS Package Number E20A, J16A,

M16A, N16E or W16A

DM54LS175W, DM74LS175M or DM74LS175N

See NS Package Number E20A, J16A,

M16A, N16E or W16A

Function Table (Each Flip-Flop)

High Level (steady state)

Low Level (steady state)

Don’t Care

Inputs

Clock

Outputs

Clear

Transition from low to high level

The level of Q before the indicated steady-state input conditions were

established.

LS175 only

1995 National Semiconductor Corporation

TL/F/6404

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6 7 8

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