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74LC32BQX_08 PDF预览

74LC32BQX_08

更新时间: 2024-11-03 12:51:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
13页 791K
描述
Low Voltage Quad 2-Input OR Gate with 5V Tolerant Inputs

74LC32BQX_08 数据手册

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March 2008  
74LCX32  
Low Voltage Quad 2-Input OR Gate with 5V Tolerant Inputs  
Features  
General Description  
5V tolerant inputs  
The LCX32 contains four 2-input OR gates. The inputs  
tolerate voltages up to 7V allowing the interface of 5V  
systems to 3V systems.  
2.3V–3.6V V specifications provided  
CC  
5.5ns t max. (V = 3.3V), 10µA I max.  
PD  
CC  
CC  
The 74LCX32 is fabricated with advanced CMOS tech-  
nology to achieve high speed operation while maintain-  
ing CMOS low power dissipation.  
Power down high impedance inputs and outputs  
24mA output drive (V = 3.0V)  
CC  
Implements proprietary noise/EMI reduction circuitry  
Latch-up performance exceeds JEDEC 78 conditions  
ESD performance:  
– Human body model > 2000V  
– Machine model > 150V  
Leadless DQFN package  
Ordering Information  
Package  
Order Number  
74LCX32M  
Number  
Package Description  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LCX32SJ  
M14D  
(1)  
74LC32BQX  
MLP14A  
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC  
MO-241, 2.5 x 3.0mm  
74LCX32MTC  
MTC14  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Note:  
1. DQFN package available in Tape and Reel only.  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
All packages are lead free per JEDEC: J-STD-020B standard.  
©1995 Fairchild Semiconductor Corporation  
74LCX32 Rev. 1.6.0  
www.fairchildsemi.com  

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