Philips Semiconductors
Product specification
4 x 4 register file; 3-state
74HC/HCT670
the location of the stored word. When the WE input is
LOW, the data is entered into the addressed location. The
addressed location remains transparent to the data while
the WE input is LOW. Data supplied at the inputs will be
read out in true (non-inverting) form from the 3-state
outputs (Q0 to Q3). Dn and Wn inputs are inhibited when
WE is HIGH.
FEATURES
• Simultaneous and independent read and write
operations
• Expandable to almost any word size and bit length
• Output capability: bus driver
• ICC category: MSI
Direct acquisition of data stored in any of the four registers
is made possible by individual read address inputs
(RA and RB). The addressed word appears at the four
outputs when the RE is LOW. Data outputs are in the high
impedance OFF-state when RE is HIGH. This permits
outputs to be tied together to increase the word capacity to
very large numbers.
GENERAL DESCRIPTION
The 74HC/HCT670 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT670 are 16-bit 3-state register files
Design of the read enable signals for the stacked devices
must ensure that there is no overlap in the LOW levels
which would cause more than one output to be active at
the same time. Parallel expansion to generate n-bit words
is accomplished by driving the enable and address inputs
of each device in parallel.
organized as 4 words of 4 bits each. Separated read and
write address inputs (RA, RB and WA, WB) and enable
inputs (RE and WE) are available, permitting simultaneous
writing into one word location and reading from another
location. The 4-bit word to be stored is presented to four
data inputs (D0 to D3). The WA and WB inputs determine
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL PARAMETER
CONDITIONS
UNIT
ns
HC
HCT
23
tPHL/ tPLH propagation delay Dn to Qn
CL = 15 pF; VCC = 5 V
23
CI
input capacitance
3.5
3.5
pF
pF
CPD
power dissipation capacitance per package
notes 1 and 2
122
124
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo)
where:
fi = input frequency in MHz
fo = output frequency in MHz
2
∑ (CL × VCC × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
;
for HCT the condition is VI = GND to VCC −1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2