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74HC541 PDF预览

74HC541

更新时间: 2024-11-18 22:53:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 92K
描述
Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer

74HC541 数据手册

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September 1983  
Revised February 1999  
MM74HC540 • MM74HC541  
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer  
In order to enhance PC board layout, the MM74HC540 and  
MM74HC541 offers a pinout having inputs and outputs on  
General Description  
The MM74HC540 and MM74HC541 3-STATE buffers uti-  
opposite sides of the package. All inputs are protected from  
lize advanced silicon-gate CMOS technology. They pos-  
damage due to static discharge by diodes to VCC and  
sess high drive current outputs which enable high speed  
ground.  
operation even when driving large bus capacitances.  
These circuits achieve speeds comparable to low power  
Schottky devices, while retaining the advantage of CMOS  
Features  
circuitry, i.e., high noise immunity, and low power consump-  
tion. Both devices have a fanout of 15 LS-TTL equivalent  
inputs.  
Typical propagation delay: 12 ns  
3-STATE outputs for connection to system buses  
Wide power supply range: 2–6V  
The MM74HC540 is an inverting buffer and the  
MM74HC541 is a non-inverting buffer. The 3-STATE con-  
trol gate operates as a two-input NOR such that if either G1  
or G2 are HIGH, all eight outputs are in the high-imped-  
ance state.  
Low quiescent current: 80 µA maximum (74HC Series)  
Output current: 6 mA  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HC540WM  
MM74HC540SJ  
MM74HC540MTC  
MM74HC540N  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
MM74HC541WM  
MM74HC541SJ  
MM74HC541MTC  
MM74HC541N  
M20B  
M20D  
MTC20  
N20A  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagrams  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Top View  
MM74HC540  
Top View  
MM74HC541  
© 1999 Fairchild Semiconductor Corporation  
DS005341.prf  
www.fairchildsemi.com  

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