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74HC4514PW PDF预览

74HC4514PW

更新时间: 2024-02-22 21:29:47
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
13页 179K
描述
HC/UH SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, PDSO24, SOT-355, 24 PIN

74HC4514PW 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOIC
包装说明:TSSOP, TSSOP24,.25针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.16
其他特性:ADDRESS LATCHES系列:HC/UH
输入调节:LATCHEDJESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:7.8 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.004 A湿度敏感等级:1
功能数量:1端子数量:24
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP24,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:69 ns传播延迟(tpd):69 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

74HC4514PW 数据手册

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Philips Semiconductors  
Product specification  
4-to-16 line decoder/demultiplexer with  
input latches  
74HC/HCT4514  
The 74HC/HCT4514 are 4-to-16 line  
FEATURES  
decoders/demultiplexers having four binary weighted  
address inputs (A0 to A3), with latches, a latch enable input  
(LE), and an active LOW enable input (E). The 16 outputs  
(Q0 to Q15) are mutually exclusive active HIGH. When LE  
is HIGH, the selected output is determined by the data on  
An. When LE goes LOW, the last data present at An are  
stored in the latches and the outputs remain stable. When  
E is LOW, the selected output, determined by the contents  
of the latch, is HIGH. At E HIGH, all outputs are LOW. The  
enable input (E) does not affect the state of the latch.  
Non-inverting outputs  
Output capability: standard  
ICC category: MSI  
GENERAL DESCRIPTION  
The 74HC/HCT4514 are high-speed Si-gate CMOS  
devices and are pin compatible with “4514” of the “4000B”  
series. They are specified in compliance with JEDEC  
standard no. 7A.  
When the “4514” is used as a demultiplexer, E is the data  
input and A0 to A3 are the address inputs.  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL  
PARAMETER  
propagation delay An to Qn  
CONDITIONS  
UNIT  
ns  
HC  
23  
HCT  
26  
tPHL/ tPLH  
CI  
CL = 15 pF; VCC = 5 V  
input capacitance  
3.5  
44  
3.5  
45  
pF  
pF  
CPD  
power dissipation capacitance per package  
notes 1 and 2  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
2
PD = CPD × VCC2 × fi +(CL × VCC × fo) where:  
fi = input frequency in MHz  
fo = output frequency in MHz  
(CL × VCC2 × fo) = sum of outputs  
CL = output load capacitance in pF  
VCC = supply voltage in V  
2. For HC the condition is VI = GND to VCC  
For HCT the condition is VI = GND to VCC 1.5 V  
ORDERING INFORMATION  
See “74HC/HCT/HCU/HCMOS Logic Package Information”.  
September 1993  
2

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