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74HC4514DB PDF预览

74HC4514DB

更新时间: 2024-01-10 00:22:17
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件
页数 文件大小 规格书
13页 179K
描述
HC/UH SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, PDSO24, SSOP-24

74HC4514DB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SSOP
包装说明:SSOP, SSOP24,.3针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.41
其他特性:ADDRESS LATCHES系列:HC/UH
输入调节:LATCHEDJESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:8.2 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.004 A湿度敏感等级:1
功能数量:1端子数量:24
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP24,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:69 ns传播延迟(tpd):69 ns
认证状态:Not Qualified座面最大高度:2 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:5.3 mmBase Number Matches:1

74HC4514DB 数据手册

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Philips Semiconductors  
Product specification  
4-to-16 line decoder/demultiplexer with  
input latches  
74HC/HCT4514  
DC CHARACTERISTICS FOR 74HCT  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: standard  
ICC category: MSI  
Note to HCT types  
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications.  
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.  
INPUT  
UNIT LOAD COEFFICIENT  
An  
LE  
E
0.65  
1.40  
1.00  
AC CHARACTERISTICS FOR 74HCT  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
Tamb (°C)  
TEST CONDITIONS  
74HCT  
SYMBOL PARAMETER  
UNIT  
WAVEFORMS  
VCC  
(V)  
+25  
40 to +85 40 to +125  
min. typ. max. min. max. min. max.  
t
PHL/ tPLH propagation delay  
An to Qn  
30  
29  
17  
7
55  
50  
40  
15  
69  
63  
50  
19  
83  
75  
60  
22  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
4.5 Fig.6  
4.5 Fig.6  
4.5 Fig.6  
4.5 Fig.6  
4.5 Fig.7  
4.5 Fig.7  
4.5 Fig.7  
tPHL/ tPLH propagation delay  
LE to Qn  
t
PHL/ tPLH propagation delay  
E to Qn  
tTHL/ tTLH output transition time  
latch enable pulse width  
HIGH  
tW  
16  
18  
3
4
20  
23  
3
24  
27  
3
set-up time  
An to LE  
tsu  
9
hold time  
An to LE  
th  
3  
September 1993  
7

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