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74HC4046APW PDF预览

74HC4046APW

更新时间： 2024-01-11 01:53:12
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
34页 470K
描述
Phase-locked-loop with VCO

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74HC4046APW 技术参数

Source Url Status Check Date：2013-06-14 00:00:00是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.14模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：5 mm湿度敏感等级：1
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.1 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mmBase Number Matches：1

74HC4046APW 数据手册

 浏览型号74HC4046APW的Datasheet PDF文件第28页浏览型号74HC4046APW的Datasheet PDF文件第29页浏览型号74HC4046APW的Datasheet PDF文件第30页浏览型号74HC4046APW的Datasheet PDF文件第32页浏览型号74HC4046APW的Datasheet PDF文件第33页浏览型号74HC4046APW的Datasheet PDF文件第34页 
Philips Semiconductors  
Product specification  
Phase-locked-loop with VCO  
74HC/HCT4046A  
PLL design example  
The VCO gain is:  
and the damping value ζ is defined as  
follows:  
˙
2fL × 2 × π  
The frequency synthesizer, used in  
the design example shown in Fig.32,  
has the following parameters:  
Kv  
=
=
----------------------------------------------  
1 + Kp × Kv × Kn × τ2  
1
0.9 – (VCC – 0.9)  
ζ =  
×
---------- -----------------------------------------------------  
2ωn (τ1 + τ2)  
Output frequency: 2 MHz to 3 MHz  
frequency steps : 100 kHz  
1 MHz  
-----------------  
3.2  
In Fig.33 the output frequency response to  
a step of input frequency is shown.  
=
× 2 π ≈ 2 × 106 r/s/V  
settling time  
overshoot  
:
:
1 ms  
< 20%  
The overshoot and settling time  
percentages are now used to determine  
ωn. From Fig.33 it can be seen that the  
damping ratio ζ = 0.45 will produce an  
overshoot of less than 20% and settle to  
within 5% at ωnt = 5. The required settling  
time is 1 ms.  
The gain of the phase  
comparator is:  
The open-loop gain is  
H (s) x G (s) = Kp × Kf × Ko × Kn.  
VCC  
Kp  
=
= 0.4 V/r.  
------------  
4 × π  
Where:  
The transfer gain of the filter is  
given by:  
Kp = phase comparator gain  
Kf = low-pass filter transfer gain  
Ko = Kv/s VCO gain  
This results in:  
1 + τ2s  
Kf =  
.
------------------------------------  
5
--  
t
5
1 + (τ1 + τ2) s  
Kn = 1/n divider ratio  
ω n  
=
=
= 5 × 103 r/s.  
--------------  
0.001  
The programmable counter ratio  
Kn can be found as follows:  
Where:  
Rewriting the equation for natural  
frequency results in:  
τ 1 = R3C2 and τ2 = R4C2.  
fout  
2 MHz  
---------------------  
100 kHz  
Nmin.  
=
=
= 20  
----------  
fstep  
Kp × Kv × Kn  
The characteristics equation is:  
1 + H (s) × G (s) = 0.  
(τ1 + τ2) =  
.
-------------------------------  
ω2n  
This results in:  
fout  
3 MHz  
---------------------  
100 kHz  
The maximum overshoot occurs at Nmax.:  
Nmax.  
=
=
= 30  
----------  
fstep  
1 + Kp × Kv × Kn × τ  
s2 +  
2s+  
0.4 × 2 × 106  
50002 × 30  
-----------------------------------------------------  
(τ1 + τ2)  
(τ 1 + τ 2 ) =  
= 0.0011 s.  
---------------------------------  
The VCO is set by the values of R1,  
R2 and C1, R2 = 10 kΩ (adjustable).  
The values can be determined using  
the information in the section  
“DESIGN CONSIDERATIONS”.  
With fo = 2.5 MHz and fL = 500 kHz  
this gives the following values  
(VCC = 5.0 V):  
Kp × Kv × Kn  
When C2 = 470 nF, then  
(τ1 + τ2) × 2 × ωn × ζ – 1  
= 0.  
-------------------------------  
(τ1 + τ2)  
R4 =  
= 315 Ω  
----------------------------------------------------------------  
Kp × Kv × Kn × C2  
The natural frequency ωn is  
defined as follows:  
now R3 can be calculated:  
Kp × Kv × Kn  
τ1  
ωn  
=
------------------------------- .  
R1 = 10 kΩ  
R2 = 10 kΩ  
R3 =  
– R4 = 2 kΩ.  
-------  
(τ1 + τ2)  
C2  
C1 = 500 pF  
1997 Nov 25  
31  
1...28293031323334

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