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74HC40105 PDF预览

74HC40105

更新时间: 2024-02-11 06:32:28
品牌 Logo 应用领域
恩智浦 - NXP 先进先出芯片
页数 文件大小 规格书
25页 203K
描述
4-bit x 16-word FIFO register

74HC40105 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.27
Is Samacsys:N最长访问时间:600 ns
周期时间:71.428 nsJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:5 mm
内存密度:64 bit内存宽度:4
湿度敏感等级:1功能数量:1
端子数量:16字数:16 words
字数代码:16工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-40 °C
组织:16X4可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

74HC40105 数据手册

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Philips Semiconductors  
Product specification  
4-bit x 16-word FIFO register  
74HC/HCT40105  
different shifting rates. This feature makes it particularly  
useful as a buffer between asynchronous systems. Each  
word position in the register is clocked by a control flip-flop,  
which stores a marker bit. A “1” signifies that the position’s  
data is filled and a “0” denotes a vacancy in that position.  
The control flip-flop detects the state of the preceding  
flip-flop and communicates its own status to the  
FEATURES  
Independent asynchronous inputs and outputs  
Expandable in either direction  
Reset capability  
Status indicators on inputs and outputs  
3-state outputs  
succeeding flip-flop. When a control flip-flop is in the “0”  
state and sees a “1” in the preceding flip-flop, it generates  
a clock pulse that transfers data from the preceding four  
data latches into its own four data latches and resets the  
preceding flip-flop to “0”. The first and last control flip-flops  
have buffered outputs. Since all empty locations “bubble”  
automatically to the input end, and all valid data ripples  
through to the output end, the status of the first control  
flip-flop (data-in ready output - DIR) indicates if the FIFO is  
full, and the status of the last flip-flop (data-out ready  
output - DOR) indicates if the FIFO contains data. As the  
earliest data is removed from the bottom of the data stack  
(output end), all data entered later will automatically ripple  
toward the output.  
Output capability: standard  
ICC category: MSI  
GENERAL DESCRIPTION  
The 74HC/HCT40105 are high-speed Si-gate CMOS  
devices and are pin compatible with the “40105” of the  
“4000B” series. They are specified in compliance with  
JEDEC standard no. 7A.  
The 74HC/HCT40105 are first-in/first-out (FIFO) “elastic”  
storage registers that can store sixteen 4-bit words. The  
“40105” is capable of handling input and output data at  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYP.  
SYMBOL  
PARAMETER  
propagation delay  
CONDITIONS  
UNIT  
HC  
HCT  
t
PHL/ tPLH  
CL = 15 pF; VCC = 5 V  
MR to DIR, DOR  
SO to Qn  
16  
37  
15  
ns  
35  
ns  
tPHL  
propagation delay  
SI to DIR  
16  
17  
33  
18  
ns  
SO to DOR  
18  
ns  
fmax  
CI  
maximum clock frequency  
input capacitance  
31  
MHz  
pF  
3.5  
3.5  
145  
CPD  
power dissipation capacitance per package notes 1 and 2  
134  
pF  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:  
fi = input frequency in MHz.  
fo = output frequency in MHz.  
(CL × VCC2 × fo) = sum of outputs  
CL = output load capacitance in pF  
VCC = supply voltage in V  
2. For HC the condition is VI = GND to VCC  
For HCT the condition is VI = GND to VCC 1.5  
1998 Jan 23  
2

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