Datasheet > 74HC193PW-Q100J

74HC193PW-Q100J

更新时间： 2024-01-30 01:25:51

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
29页	190K
描述
74HC(T)193-Q100 - Presettable synchronous 4-bit binary up/down counter TSSOP 16-Pin

阅读下载

获取价格

如果您发现信息不准确，欢迎纠错

74HC193PW-Q100J 技术参数

74HC193-Q100; 74HCT193-Q100

NXP Semiconductors

Presettable synchronous 4-bit binary up/down counter

(1)

(2)

CPU

(2)

CPD

TCU

TCD

CLEAR PRESET

(1) Clear overrides load, data and count inputs.

COUNT UP

COUNT DOWN

001aag411

(2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock input

(CPU) must be HIGH.

Sequence

Clear (reset outputs to zero);

load (preset) to binary thirteen;

count up to fourteen, fifteen, terminal count up, zero, one and two;

count down to one, zero, terminal count down, fifteen, fourteen and thirteen.

Fig 7. Typical clear, load and count sequence

74HC_HCT139_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 12 July 2013

7 of 29

1...4 5 678 9 10...29

下载PDF

型号	品牌	描述	获取价格	数据表
74HC193-Q100	NEXPERIA	Presettable synchronous 4-bit binary up/down counter	获取价格
74HC194	NXP	4-bit bidirectional universal shift register	获取价格
74HC194D	NXP	4-bit bidirectional universal shift register	获取价格
74HC194D,652	NXP	74HC(T)194 - 4-bit bidirectional universal shift register SOP 16-Pin	获取价格
74HC194D,653	NXP	74HC(T)194 - 4-bit bidirectional universal shift register SOP 16-Pin	获取价格
74HC194D/T3	NXP	IC HC/UH SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT,	获取价格