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74FCT823ATQG8 PDF预览

74FCT823ATQG8

更新时间: 2024-01-24 19:03:59
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
7页 516K
描述
QSOP-24, Reel

74FCT823ATQG8 数据手册

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IDT74FCT823AT/CT  
HIGH-PERFORMANCECMOSBUSINTERFACEREGISTER  
INDUSTRIALTEMPERATURERANGE  
ABSOLUTEMAXIMUMRATINGS(1)  
PINCONFIGURATION  
Symbol  
Description  
Max  
Unit  
V
(2)  
VTERM  
Terminal Voltage with Respect to GND  
–0.5 to +7  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
1
OE  
D0  
VCC  
Y0  
(3)  
VTERM  
Terminal Voltage with Respect to GND –0.5 to VCC+0.5  
V
2
3
4
TSTG  
IOUT  
Storage Temperature  
DC Output Current  
–65 to +150  
–60 to +120  
° C  
mA  
D1  
D2  
Y1  
Y2  
NOTES:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability. No terminal voltage may exceed  
Vcc by +0.5V unless otherwise noted.  
D3  
D4  
D5  
Y3  
Y4  
Y5  
5
6
7
8
9
2. Inputs and Vcc terminals only.  
3. Output and I/O terminals only.  
D6  
D7  
Y6  
Y7  
CAPACITANCE (TA = +25°C, F = 1.0MHz)  
Symbol  
Parameter(1)  
Input Capacitance  
Output Capacitance  
Conditions  
Typ.  
Max. Unit  
D8  
Y8  
10  
11  
CIN  
VIN = 0V  
6
10  
12  
pF  
pF  
CLR  
EN  
CP  
COUT  
VOUT = 0V  
8
GND  
12  
NOTE:  
1. This parameter is measured at characterization but not tested.  
SOIC/ QSOP  
TOP VIEW  
PINDESCRIPTION  
FUNCTIONTABLE(1)  
Internal/  
Pin Names  
I/O  
Description  
Inputs  
EN  
L
Outputs  
Dx  
I
I
D Flip-Flop Data Inputs  
OE  
H
H
H
L
CLR  
H
H
L
Dx  
L
CP  
X
X
X
X
Qx  
Yx  
Z
Function  
CLR  
When the clear input is LOW and OE is LOW, the  
Qx outputs are LOW. When the clear input is HIGH,  
data can be entered into the register.  
L
H
HighZ  
L
H
X
X
X
X
L
Z
CP  
I
Clock Pulse for the Register; enters data into the  
register on the LOW-to-HIGH transition.  
X
L
Z
Clear  
Hold  
Load  
L
X
L
L
Yx  
O
I
Register 3-State Outputs  
H
L
H
H
H
H
H
H
H
N C  
NC  
L
Z
EN  
Clock Enable. When the clock enable is LOW, data  
on the Dx output is transferred to the Qx output on the  
LOW-to-HIGH transition. When the clock enable is  
HIGH, the Qx outputs do not change state, regardless  
of the data or clock input transitions.  
H
NC  
Z
H
H
L
L
L
H
L
H
Z
L
L
L
L
L
H
H
H
OE  
I
Output Control. When the OE is HIGH, the Yx  
outputs are in the high-impedance state. When the  
OE is LOW, the TRUE register data is present at the  
Yx outputs.  
NOTE:  
1. H = HIGH Voltage Level  
X = Don’t Care  
L = LOW Voltage Level  
NC = No Change  
= LOW-to-HIGH Transition  
Z = High Impedance  
2

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