74FCT388915T70JI

更新时间： 2024-02-03 07:11:57

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艾迪悌 - IDT		时钟驱动器逻辑集成电路输出元件
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74FCT388915T70JI 数据手册

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IDT74FCT388915T

3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)

COMMERCIALTEMPERATURERANGE

CPU

CARD

CMMU

CPU

CMMU

FCT388915T

PLL

CLOCK

SYSTEM

CLOCK

SOURCE

CMMU

CPU

CARD

CMMU

CPU

CMMU

FCT388915T

PLL

CMMU

DISTRIBUTE

CLOCK @f

CLOCK @2f

at point of use

FCT388915T

PLL

MEMORY

CONTROL

MEMORY

CARDS

CLOCK @2f

at point of use

Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication

and Low Board-to-Board skew

FCT388915TSYSTEMLEVELTESTING

FUNCTIONALITY

Theserelationshipscanbeseenintheblockdiagram. Arecommendedtest

configurationwouldbetouseSYNC0orSYNC1asthetestclockinput,andtie

PLL_ENandREF_SELtogetherandconnectthemtothetestselectlogic.

WhenthePLL_ENpinisLOW,thePLLisbypassedandtheFCT388915T

isinlowfrequency"testmode". Intestmode(withFREQ_SELHIGH),the2Q

outputisinvertedfromtheselectedSYNCinput,andtheQoutputsaredivide-

by-2(negativeedgetriggered)oftheSYNCinput,andtheQ/2outputisdivide-

by-4(negativeedgetriggered). WithFREQ_SELLOWthe2Qoutputisdivide-

by-2oftheSYNC,theQoutputsdivide-by-4,andtheQ/2outputdivide-by-8.

Thisfunctionalityisneededsincemostboard-leveltestersrunat1MHzor

below,andtheFCT388915Tcannotlockontothatlowofaninputfrequency.

Inthetestmodedescribedabove,anytestfrequencytestcanbeused.

1...5 6 789 10

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