74FCT388915T70JI

更新时间： 2024-02-01 19:45:09

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器逻辑集成电路输出元件
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10页	154K
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74FCT388915T70JI 数据手册

浏览型号74FCT388915T70JI的Datasheet PDF文件第10页

IDT74FCT388915T

3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)

COMMERCIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

6.0V

VCC

V_CC

VCC

GND

100Ω

500Ω

VOUT

Pulse

Generator

Pulse

Generator

D.U.T.

20pF

100Ω

50Ω to VCC/2, CL = 20pF

Enable and Disable Test Circuit

1.5V

SYNC INPUT

(SYNC (1) or

SYNC (0))

CYCLE

SYNC INPUT

tPD

VCC/2

FEEDBACK

INPUT

Q/2 OUTPUT

SKEWf

SKEWr

VCC/2

SKEWALL

Q0-Q4

OUTPUTS

CYCLE "Q" OUTPUTS

VCC/2

Q5 OUTPUT

2Q OUTPUT

Propagation Delay, Output Skew

(These waveforms represent the configuration of Figure 3a)

NOTES:

1. The FCT388915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle.

2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as ± deviation around a center point.

3. If a Q ouput is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q output would run at twice

the SYNC frequency and the Q/2 output would run at half the SYNC frequency.

ENABLE

DISABLE

SWITCHPOSITION

CONTROL

INPUT

1.5V

Test

Switch

tPZL

tPLZ

Disable Low

Enable Low

1.5V

OUTPUT

NORMALLY

LOW

SWITCH

0.3V

VOL

Disable High

Enable High

GND

tPZH

tPHZ

VOH

OUTPUT

NORMALLY

HIGH

SWITCH

GND

1.5V

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

2. Pulse Generator for All Pulses: tF ≤ 2.5ns; tR ≤ 2.5ns.

1...6 7 8910

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