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74F14SC_NL PDF预览

74F14SC_NL

更新时间: 2024-11-16 19:48:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电二极管逻辑集成电路
页数 文件大小 规格书
5页 64K
描述
Inverter, F/FAST Series, 6-Func, 1-Input, TTL, PDSO14, 0.150 INCH, LEAD FREE, MS-120, SOIC-14

74F14SC_NL 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84系列:F/FAST
JESD-30 代码:R-PDSO-G14JESD-609代码:e3/e4
长度:8.65 mm逻辑集成电路类型:INVERTER
功能数量:6输入次数:1
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):11.5 ns
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:MATTE TIN/NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mmBase Number Matches:1

74F14SC_NL 数据手册

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March 1988  
Revised November 2005  
74F14  
Hex Inverter Schmitt Trigger  
totem-pole output. The Schmitt trigger uses positive feed  
back to effectively speed-up slow input transition, and pro-  
vide different input threshold voltages for positive and neg-  
ative-going transitions. This hysteresis between the  
positive-going and negative-going input thresholds (typi-  
cally 800 mV) is determined internally by resistor ratios and  
is essentially insensitive to temperature and supply voltage  
variations.  
General Description  
The 74F14 contains six logic inverters which accept stan-  
dard TTL input signals and provide standard TTL output  
levels. They are capable of transforming slowly changing  
input signals into sharply defined, jitter-free output signals.  
In addition, they have a greater noise margin than conven-  
tional inverters.  
Each circuit contains a Schmitt trigger followed by a Dar-  
lington level shifter and a phase splitter driving a TTL  
Ordering Code:  
Order Number Package Number  
Package Description  
74F14SC  
74F14SJ  
74F14PC  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Unit Loading/Fan Out  
Function Table  
Input IIH/IIL  
Input  
Output  
U.L.  
Pin Names Description  
Output IOH/IOL  
HIGH/LOW  
1.0/1.0  
A
L
O
H
L
In  
Input  
20 µA/0.6 mA  
1 mA/20 mA  
H
On  
Output  
50/33.3  
H = HIGH Voltage Level  
L = LOW Voltage Level  
© 2005 Fairchild Semiconductor Corporation  
DS009461  
www.fairchildsemi.com  

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