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74F02SJCX PDF预览

74F02SJCX

更新时间: 2024-11-06 03:56:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 逻辑集成电路光电二极管
页数 文件大小 规格书
5页 64K
描述
Quad 2-Input NOR Gate

74F02SJCX 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:0.300 INCH, EIAJ, PLASTIC, SOP-14针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.58Is Samacsys:N
系列:F/FASTJESD-30 代码:R-PDSO-G14
长度:10.1 mm逻辑集成电路类型:NOR GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):5.3 ns
认证状态:Not Qualified座面最大高度:2.1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:5.3 mm
Base Number Matches:1

74F02SJCX 数据手册

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April 1988  
Revised September 2000  
74F02  
Quad 2-Input NOR Gate  
General Description  
This device contains four independent gates, each of which  
performs the logic NOR function.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F02SC  
74F02SJ  
74F02PC  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Unit Loading/Fan Out  
Input IIH/IIL  
U.L.  
Pin Names  
Description  
Output IOH/IOL  
HIGH/LOW  
1.0/1.0  
An, Bn  
On  
Inputs  
Outputs  
20 µA/0.6 mA  
1 mA/20 mA  
50/33.3  
© 2000 Fairchild Semiconductor Corporation  
DS009455  
www.fairchildsemi.com  

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