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74AUP1G885GD PDF预览

74AUP1G885GD

更新时间: 2024-02-06 07:51:43
品牌 Logo 应用领域
恩智浦 - NXP 栅极逻辑集成电路石英晶振光电二极管
页数 文件大小 规格书
19页 99K
描述
Low-power dual function gate

74AUP1G885GD 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:VSON,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.63
Is Samacsys:N系列:AUP/ULP/V
JESD-30 代码:R-PDSO-N8JESD-609代码:e3
长度:1.95 mm逻辑集成电路类型:XOR GATE
湿度敏感等级:1功能数量:2
输入次数:3端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):23.7 ns
认证状态:Not Qualified座面最大高度:0.5 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.1 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:1 mm
Base Number Matches:1

74AUP1G885GD 数据手册

 浏览型号74AUP1G885GD的Datasheet PDF文件第3页浏览型号74AUP1G885GD的Datasheet PDF文件第4页浏览型号74AUP1G885GD的Datasheet PDF文件第5页浏览型号74AUP1G885GD的Datasheet PDF文件第7页浏览型号74AUP1G885GD的Datasheet PDF文件第8页浏览型号74AUP1G885GD的Datasheet PDF文件第9页 
74AUP1G885  
NXP Semiconductors  
Low-power dual function gate  
Table 7.  
Static characteristics …continued  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
VOL  
LOW-level output voltage  
VI = VIH or VIL  
IO = 20 µA; VCC = 0.8 V to 3.6 V  
IO = 1.1 mA; VCC = 1.1 V  
IO = 1.7 mA; VCC = 1.4 V  
IO = 1.9 mA; VCC = 1.65 V  
IO = 2.3 mA; VCC = 2.3 V  
IO = 3.1 mA; VCC = 2.3 V  
IO = 2.7 mA; VCC = 3.0 V  
IO = 4.0 mA; VCC = 3.0 V  
VI = GND to 3.6 V; VCC = 0 V to 3.6 V  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1  
V
0.3 × VCC  
0.31  
0.31  
0.31  
0.44  
0.31  
0.44  
±0.1  
±0.2  
±0.2  
V
V
V
V
V
V
V
II  
input leakage current  
µA  
µA  
µA  
IOFF  
IOFF  
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V  
additional power-off  
leakage current  
VI or VO = 0 V to 3.6 V;  
CC = 0 V to 0.2 V  
V
ICC  
supply current  
VI = GND or VCC; IO = 0 A;  
CC = 0.8 V to 3.6 V  
-
-
-
-
0.5  
40  
µA  
µA  
V
[1]  
ICC  
additional supply current  
VI = VCC 0.6 V; IO = 0 A;  
CC = 3.3 V  
V
CI  
input capacitance  
output capacitance  
VCC = 0 V to 3.6 V; VI = GND or VCC  
VO = GND; VCC = 0 V  
-
-
0.6  
1.3  
-
-
pF  
pF  
CO  
Tamb = 40 °C to +85 °C  
VIH HIGH-level input voltage  
VCC = 0.8 V  
0.70 × VCC  
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 0.8 V  
0.65 × VCC  
-
1.6  
-
2.0  
-
VIL  
LOW-level input voltage  
-
-
-
-
0.30 × VCC  
0.35 × VCC  
0.7  
VCC = 0.9 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
0.9  
VOH  
HIGH-level output voltage VI = VIH or VIL  
IO = 20 µA; VCC = 0.8 V to 3.6 V  
V
CC 0.1  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = 1.1 mA; VCC = 1.1 V  
IO = 1.7 mA; VCC = 1.4 V  
IO = 1.9 mA; VCC = 1.65 V  
IO = 2.3 mA; VCC = 2.3 V  
IO = 3.1 mA; VCC = 2.3 V  
IO = 2.7 mA; VCC = 3.0 V  
IO = 4.0 mA; VCC = 3.0 V  
0.7 × VCC  
1.03  
1.30  
1.97  
1.85  
2.67  
2.55  
74AUP1G885_5  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 05 — 26 June 2009  
6 of 19  

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