5秒后页面跳转
74AUP1G08GW-Q100,125 PDF预览

74AUP1G08GW-Q100,125

更新时间: 2024-02-15 20:13:00
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
15页 107K
描述
AND Gate, AUP/ULP/V Series, 1-Func, 2-Input, CMOS, PDSO5

74AUP1G08GW-Q100,125 技术参数

生命周期:Active包装说明:TSSOP,
Reach Compliance Code:unknown风险等级:5.59
系列:AUP/ULP/VJESD-30 代码:R-PDSO-G5
长度:2.05 mm逻辑集成电路类型:AND GATE
功能数量:1输入次数:2
端子数量:5最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):24 ns
筛选级别:AEC-Q100座面最大高度:1.1 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.1 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:1.25 mm
Base Number Matches:1

74AUP1G08GW-Q100,125 数据手册

 浏览型号74AUP1G08GW-Q100,125的Datasheet PDF文件第3页浏览型号74AUP1G08GW-Q100,125的Datasheet PDF文件第4页浏览型号74AUP1G08GW-Q100,125的Datasheet PDF文件第5页浏览型号74AUP1G08GW-Q100,125的Datasheet PDF文件第7页浏览型号74AUP1G08GW-Q100,125的Datasheet PDF文件第8页浏览型号74AUP1G08GW-Q100,125的Datasheet PDF文件第9页 
74AUP1G08-Q100  
NXP Semiconductors  
Low-power 2-input AND gate  
Table 7.  
Static characteristics …continued  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
ICC  
supply current  
VI = GND or VCC; IO = 0 A;  
VCC = 0.8 V to 3.6 V  
-
-
0.9  
A  
[1]  
ICC  
additional supply current  
VI = VCC 0.6 V; IO = 0 A;  
-
-
50  
A  
VCC = 3.3 V  
Tamb = 40 C to +125 C  
VIH HIGH-level input voltage  
VCC = 0.8 V  
0.75 VCC  
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 0.8 V  
0.70 VCC  
-
1.6  
-
2.0  
-
VIL  
LOW-level input voltage  
-
-
-
-
0.25 VCC  
0.30 VCC  
0.7  
VCC = 0.9 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
0.9  
VOH  
HIGH-level output voltage VI = VIH or VIL  
IO = 20 A; VCC = 0.8 V to 3.6 V  
VCC 0.11 -  
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = 1.1 mA; VCC = 1.1 V  
IO = 1.7 mA; VCC = 1.4 V  
IO = 1.9 mA; VCC = 1.65 V  
IO = 2.3 mA; VCC = 2.3 V  
IO = 3.1 mA; VCC = 2.3 V  
IO = 2.7 mA; VCC = 3.0 V  
IO = 4.0 mA; VCC = 3.0 V  
VI = VIH or VIL  
0.6 VCC  
0.93  
-
-
-
-
-
-
-
1.17  
1.77  
1.67  
2.40  
2.30  
VOL  
LOW-level output voltage  
IO = 20 A; VCC = 0.8 V to 3.6 V  
IO = 1.1 mA; VCC = 1.1 V  
IO = 1.7 mA; VCC = 1.4 V  
IO = 1.9 mA; VCC = 1.65 V  
IO = 2.3 mA; VCC = 2.3 V  
IO = 3.1 mA; VCC = 2.3 V  
IO = 2.7 mA; VCC = 3.0 V  
IO = 4.0 mA; VCC = 3.0 V  
VI = GND to 3.6 V; VCC = 0 V to 3.6 V  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11  
V
0.33 VCC  
0.41  
V
V
0.39  
V
0.36  
V
0.50  
V
0.36  
V
0.50  
V
II  
input leakage current  
0.75  
0.75  
0.75  
A  
A  
A  
IOFF  
IOFF  
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V  
additional power-off  
leakage current  
VI or VO = 0 V to 3.6 V;  
VCC = 0 V to 0.2 V  
ICC  
supply current  
VI = GND or VCC; IO = 0 A;  
VCC = 0.8 V to 3.6 V  
-
-
-
-
1.4  
75  
A  
A  
[1]  
ICC  
additional supply current  
VI = VCC 0.6 V; IO = 0 A;  
VCC = 3.3 V  
[1] One input at VCC 0.6 V, other input at VCC or GND.  
74AUP1G08_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 1 — 31 January 2013  
6 of 15  

与74AUP1G08GW-Q100,125相关器件

型号 品牌 描述 获取价格 数据表
74AUP1G08GW-Q100H NXP 74AUP1G08-Q100 - Low-power 2-input AND gate TSSOP 5-Pin

获取价格

74AUP1G08GX NEXPERIA Low-power 2-input AND gateProduction

获取价格

74AUP1G08-Q100 NEXPERIA Low-power 2-input AND gate

获取价格

74AUP1G08SE DIODES SINGLE 2 INPUT POSITIVE AND GATE

获取价格

74AUP1G08SE-7 DIODES SINGLE 2 INPUT POSITIVE AND GATE

获取价格

74AUP1G09 NXP Low-power 2-input AND gate with open-drain

获取价格