Datasheet > 74AUP1G07GX

74AUP1G07GX

更新时间： 2023-09-03 20:29:38

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
18页	275K
描述
Low-power buffer with open-drain outputProduction

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74AUP1G07GX 数据手册

74AUP1G07

Low-power buffer with open-drain output

Rev. 11.1 — 11 July 2023

Product data sheet

1. General description

The 74AUP1G07 is a single buffer with open-drain output.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures a very low static and dynamic power consumption across the entire V_CCrange

from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the damaging backflow current through the device when it is

powered down.

2. Features and benefits

•

Wide supply voltage range from 0.8 V to 3.6 V

•

High noise immunity

CMOS low power dissipation

Complies with JEDEC standards:

•

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

•

Low static power consumption; I_CC= 0.9 μA (maximum)

Latch-up performance exceeds 100 mA per JESD 78 Class II

Overvoltage tolerant inputs to 3.6 V

Low noise overshoot and undershoot < 10 % of V_CC

I_OFFcircuitry provides partial Power-down mode operation

Multiple package options

ESD protection:

•

HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

•

Specified from -40 °C to +85 °C and -40 °C to +125 °C

12 3 4 5 6 7...18

下载PDF

与74AUP1G07GX相关器件

型号	品牌	描述	获取价格	数据表
74AUP1G07GX4	NEXPERIA	Low-power buffer with open-drain outputProduction	获取价格
74AUP1G07SE	DIODES	SINGLE BUFFER/DRIVER WITH OPEN DRAIN OUTPUT	获取价格
74AUP1G07SE-7	DIODES	SINGLE BUFFER/DRIVER WITH OPEN DRAIN OUTPUT	获取价格
74AUP1G08	NXP	Low-power 2-input AND gate	获取价格
74AUP1G08	DIODES	SINGLE 2 INPUT POSITIVE AND GATE	获取价格
74AUP1G0832	NXP	Low-power 3-input AND-OR gate	获取价格