Datasheet > 逻辑 > 栅极> 74AUP1G08

74AUP1G08

更新时间： 2024-11-29 04:00:55

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
17页	84K
描述
Low-power 2-input AND gate

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74AUP1G08 数据手册

74AUP1G08

Low-power 2-input AND gate

Rev. 02 — 29 June 2006

Product data sheet

1. General description

The 74AUP1G08 is a high-performance, low-power, low-voltage, Si-gate CMOS device,

superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V_CCrange from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 0.8 V to 3.6 V.

This device is fully speciﬁed for partial Power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

The 74AUP1G08 provides the single 2-input AND function.

2. Features

■ Wide supply voltage range from 0.8 V to 3.6 V

■ High noise immunity

■ Complies with JEDEC standards:

◆ JESD8-12 (0.8 V to 1.3 V)

◆ JESD8-11 (0.9 V to 1.65 V)

◆ JESD8-7 (1.2 V to 1.95 V)

◆ JESD8-5 (1.8 V to 2.7 V)

◆ JESD8-B (2.7 V to 3.6 V)

■ ESD protection:

◆ HBM JESD22-A114-C Class 3A. Exceeds 5000 V

◆ MM JESD22-A115-A exceeds 200 V

◆ CDM JESD22-C101-C exceeds 1000 V

■ Low static power consumption; I_CC= 0.9 µA (maximum)

■ Latch-up performance exceeds 100 mA per JESD 78 Class II

■ Inputs accept voltages up to 3.6 V

■ Low noise overshoot and undershoot < 10 % of V_CC

■ I_OFFcircuitry provides partial Power-down mode operation

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

12 3 4 5 6 7...17

中文翻译

下载PDF

与74AUP1G08相关器件

型号	品牌	获取价格	描述	数据表
74AUP1G0832	NXP	获取价格	Low-power 3-input AND-OR gate
74AUP1G0832GF	NXP	获取价格	Low-power 3-input AND-OR gate
74AUP1G0832GM	NXP	获取价格	Low-power 3-input AND-OR gate
74AUP1G0832GM	NEXPERIA	获取价格	Low-power 3-input AND-OR gateProduction
74AUP1G0832GM,132	NXP	获取价格	74AUP1G0832 - Low-power 3-input AND-OR gate SON 6-Pin
74AUP1G0832GN	NEXPERIA	获取价格	Low-power 3-input AND-OR gateProduction
74AUP1G0832GS	NXP	获取价格	AUP/ULP/V SERIES, 3-INPUT AND-OR GATE, PDSO6, 1 X 1 MM, 0.35 MM HEIGHT, 0.35 MM PITCH, SOT
74AUP1G0832GS	NEXPERIA	获取价格	Low-power 3-input AND-OR gateProduction
74AUP1G0832GS,132	NXP	获取价格	74AUP1G0832 - Low-power 3-input AND-OR gate
74AUP1G0832GW	NXP	获取价格	Low-power 3-input AND-OR gate