5秒后页面跳转
74AUP1G07GM-G PDF预览

74AUP1G07GM-G

更新时间: 2024-02-22 03:56:16
品牌 Logo 应用领域
恩智浦 - NXP 线路驱动器或接收器驱动程序和接口接口集成电路
页数 文件大小 规格书
16页 84K
描述
暂无描述

74AUP1G07GM-G 数据手册

 浏览型号74AUP1G07GM-G的Datasheet PDF文件第6页浏览型号74AUP1G07GM-G的Datasheet PDF文件第7页浏览型号74AUP1G07GM-G的Datasheet PDF文件第8页浏览型号74AUP1G07GM-G的Datasheet PDF文件第10页浏览型号74AUP1G07GM-G的Datasheet PDF文件第11页浏览型号74AUP1G07GM-G的Datasheet PDF文件第12页 
74AUP1G07  
NXP Semiconductors  
Low-power buffer with open-drain output  
Table 8.  
Dynamic characteristics …continued  
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.  
Symbol Parameter  
Conditions  
25 °C  
40 °C to +125 °C  
Unit  
Min  
Typ[1]  
Max  
Min  
Max  
Max  
(85 °C) (125 °C)  
CL = 5 pF, 10 pF, 15 pF and 30 pF  
CPD power dissipation fi = 1 MHz;  
capacitance VI = GND to VCC  
[3]  
VCC = 0.8 V  
-
-
-
-
-
-
0.5  
0.6  
0.6  
0.7  
0.9  
1.2  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF  
pF  
pF  
pF  
pF  
pF  
VCC = 1.1 V to 1.3 V  
VCC = 1.4 V to 1.6 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
[1] All typical values are measured at nominal VCC  
.
[2] tpd is the same as tPZL and tPLZ  
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
Σ(CL × VCC2 × fo) = sum of the outputs.  
12. Waveforms  
V
I
V
A input  
M
GND  
t
t
PZL  
PLZ  
V
CC  
Y output  
V
M
V
V
X
OL  
mna626  
Measurement points are given in Table 9.  
Logic level: VOL is the typical output voltage drop that occur with the output load.  
Fig 7. The data input (A) to output (Y) propagation delays  
Table 9.  
Measurement points  
Supply voltage  
VCC  
Input  
Output  
VM  
VM  
VX  
0.8 V to 1.6 V  
1.65 V to 2.7 V  
3.0 V to 3.6 V  
0.5 × VCC  
0.5 × VCC  
0.5 × VCC  
0.5 × VCC  
0.5 × VCC  
0.5 × VCC  
VOL + 0.1 V  
VOL + 0.15 V  
VOL + 0.3 V  
74AUP1G07_2  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 02 — 14 June 2007  
9 of 16  

与74AUP1G07GM-G相关器件

型号 品牌 描述 获取价格 数据表
74AUP1G07GM-H NXP IC AUP/ULP/V SERIES, 1-INPUT NON-INVERT GATE, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC,

获取价格

74AUP1G07GN NXP Low-power buffer with open-drain output

获取价格

74AUP1G07GN NEXPERIA Low-power buffer with open-drain outputProduction

获取价格

74AUP1G07GS NXP Low-power buffer with open-drain output

获取价格

74AUP1G07GS NEXPERIA Low-power buffer with open-drain outputProduction

获取价格

74AUP1G07GW NEXPERIA Low-power buffer with open-drain outputProduction

获取价格