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74ACT399SCX_NL PDF预览

74ACT399SCX_NL

更新时间: 2024-11-15 19:59:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
9页 98K
描述
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 4-Bit, True Output, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16

74ACT399SCX_NL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.61
其他特性:FOUR 2:1 MUX FOLLOWED BY REGISTER系列:ACT
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大I(ol):0.024 A
湿度敏感等级:1位数:4
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:9.5 ns
传播延迟(tpd):9.5 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:160 MHz
Base Number Matches:1

74ACT399SCX_NL 数据手册

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June 1988  
Revised October 2000  
74AC399 74ACT399  
Quad 2-Port Register  
General Description  
Features  
The AC/ACT399 is the logical equivalent of a quad 2-input  
multiplexer feeding into four edge-triggered flip-flops. A  
common Select input determines which of the two 4-bit  
words is accepted. The selected data enters the flip-flop on  
the rising edge of the clock.  
ICC reduced by 50%  
Select inputs from two data sources  
Fully positive edge-triggered operation  
Outputs source/sink 24 mA  
AC/ACT399 has TTL-compatible inputs  
Ordering Code:  
Order Number Package Number  
Package Description  
74AC399SC  
74AC399PC  
74ACT399SC  
74ACT399SJ  
74ACT399MTC  
74ACT399PC  
M16A  
N16E  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
Common Select Input  
Clock Pulse Input  
S
CP  
I
0aI0d  
Data Inputs from Source 0  
Data Inputs from Source 1  
Register True Outputs  
I1aI1d  
QaQd  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 2000 Fairchild Semiconductor Corporation  
DS009789  
www.fairchildsemi.com  

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