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74ACQ374SCX PDF预览

74ACQ374SCX

更新时间: 2024-11-24 21:13:23
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
12页 221K
描述
AC SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, SOIC-20

74ACQ374SCX 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.12
其他特性:MAX VOLP = 1.5V AT VCC = 5V, TA = 25 DEGREE C; MAX OUTPUT SKEW = 1000PS系列:AC
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:70000000 Hz
最大I(ol):0.012 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL电源:3.3/5 V
传播延迟(tpd):13.5 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:7.5 mm
Base Number Matches:1

74ACQ374SCX 数据手册

 浏览型号74ACQ374SCX的Datasheet PDF文件第2页浏览型号74ACQ374SCX的Datasheet PDF文件第3页浏览型号74ACQ374SCX的Datasheet PDF文件第4页浏览型号74ACQ374SCX的Datasheet PDF文件第5页浏览型号74ACQ374SCX的Datasheet PDF文件第6页浏览型号74ACQ374SCX的Datasheet PDF文件第7页 
March 1993  
54ACQ/74ACQ374 54ACTQ/74ACTQ374  
#
Quiet Series Octal D Flip-Flop  
with TRI-STATE Outputs  
É
General Description  
Features  
Y
CC  
I
and I  
reduced by 50%  
OZ  
The ’ACQ/’ACTQ374 is a high-speed, low-power octal D-  
type flip-flop featuring separate D-type inputs for each flip-  
flop and TRI-STATE outputs for bus-oriented applications. A  
buffered Clock (CP) and Output Enable (OE) are common to  
all flip-flops.  
Y
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Y
Y
Y
Y
Guaranteed pin-to-pin skew AC performance  
Improved latch-up immunity  
The ’ACQ/’ACTQ374 utilizes Quiet Series technology to  
guarantee quiet output switching and improve dynamic  
threshold performance. FACT Quiet SeriesTM features  
GTOTM output control and undershoot corrector in addition  
to a split ground bus for superior performance.  
Buffered positive edge-triggered clock  
TRI-STATE outputs drive bus lines or buffer memory  
address registers  
Y
Y
Y
Y
Outputs source/sink 24 mA  
Faster prop delays than the standard ’AC/’ACT374  
4 kV minimum ESD immunity  
Standard Military Drawing (SMD)  
Ð ’ACTQ374: 5962-92189  
Ð ’ACQ374: 5962-92179  
Logic Symbols  
Connection Diagrams  
Pin Assignment for DIP,  
Flatpak, QSOP and SOIC  
IEEE/IEC  
TL/F/10238–1  
TL/F/10238–3  
TL/F/10238–2  
Pin Assignment  
for LCC  
Pin Names  
Description  
Data Inputs  
D D  
0
7
CP  
OE  
Clock Pulse Input  
TRI-STATE Output Enable Input  
TRI-STATE Outputs  
O O  
0
7
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
FACTTM, FACT Quiet SeriesTM, and GTOTM are trademarks of National Semiconductor Corporation.  
TL/F/10238–4  
C
1995 National Semiconductor Corporation  
TL/F/10238  
RRD-B30M75/Printed in U. S. A.  

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