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74AC02_01 PDF预览

74AC02_01

更新时间: 2024-11-20 04:28:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
页数 文件大小 规格书
8页 184K
描述
QUAD 2-INPUT NOR GATE

74AC02_01 数据手册

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74AC02  
QUAD 2-INPUT NOR GATE  
HIGH SPEED: t = 4.2ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 2µA(MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
50TRANSMISSION LINE DRIVING  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
OH  
OL  
ORDER CODES  
PACKAGE  
BALANCED PROPAGATION DELAYS:  
TUBE  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
DIP  
SOP  
74AC02B  
74AC02M  
V
74AC02MTR  
74AC02TTR  
CC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 02  
TSSOP  
IMPROVED LATCH-UP IMMUNITY  
The internal circuit is composed of 3 stages  
including buffer output, which enables high noise  
immunity and stable output.  
DESCRIPTION  
The 74AC02 is an advanced high-speed CMOS  
QUAD 2-INPUT NOR GATE fabricated with  
sub-micron silicon gate and double-layer metal  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
2
wiring C MOS tecnology.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/8  

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