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74AC00MT PDF预览

74AC00MT

更新时间: 2024-01-27 00:02:32
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
8页 201K
描述
AC SERIES, QUAD 2-INPUT NAND GATE, PDSO14, MICRO, SO-14

74AC00MT 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.22系列:AC
JESD-30 代码:R-PDSO-G14长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):11 ns
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

74AC00MT 数据手册

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74AC00  
QUAD 2-INPUT NAND GATE  
HIGH SPEED: t = 4ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 2µA(MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
TUBE  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
DIP  
SOP  
74AC00B  
74AC00M  
V
CC  
74AC00MTR  
74AC00TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 00  
IMPROVED LATCH-UP IMMUNITY  
TSSOP  
The internal circuit is composed of 3 stages in-  
cluding buffer output, which enables high noise  
immunity nd stable output.  
All inps and outputs are equipped with protec-  
tion circuits against static discharge, giving them  
V ESD immunity and transient excess voltage.  
DESCRIPTION  
The 74AC00 is an advanced high-speed CMOS  
QUAD 2-INPUT NAND GATE fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS tecnology.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/8  

74AC00MT 替代型号

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