Datasheet > 逻辑 > 总线驱动器/收发器> 74ABT821PWDH

74ABT821PWDH

更新时间： 2024-01-31 15:53:37

品牌	Logo	应用领域
恩智浦 - NXP		触发器
页数	文件大小	规格书
6页	72K
描述
10-bit D-type flip-flop; positive-edge trigger 3-State

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数据手册

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74ABT821PWDH 数据手册

Philips Semiconductors

Product specification

10-bit D-type flip-flop; positive-edge trigger

(3-State)

74ABT821

LOGIC SYMBOL

LOGIC SYMBOL (IEEE/IEC)

10 11

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9

23 22 21 20 19 18 17 16 15 14

SA00224

SA00225

FUNCTION TABLE

INPUTS

INTERNAL

OUTPUTS

Q0 – Q9

OPERATING MODE

↑

Load and read register

Hold

↑

Disable outputs

High voltage level

NC= No change

High voltage level one set-up time

prior to the Low-to-High clock transition

Low voltage level

Low voltage level one set-up time

prior to the Low-to-High clock transition

↑

Don’t care

High impedance “off” state

Low to High clock transition

↑

Not a Low-to-High clock transition

LOGIC DIAGRAM

CP Q

SA00226

1995 Sep 06

123 4 5 6

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