5秒后页面跳转
74LS08 PDF预览

74LS08

更新时间: 2024-01-27 09:37:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
5页 63K
描述
Quad 2-Input AND Gates

74LS08 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:DIP, DIP14,.3
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.91JESD-30 代码:R-PDIP-T14
JESD-609代码:e0逻辑集成电路类型:AND GATE
湿度敏感等级:2A端子数量:14
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):250
电源:5 V施密特触发器:NO
子类别:Gates标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
Base Number Matches:1

74LS08 数据手册

 浏览型号74LS08的Datasheet PDF文件第2页浏览型号74LS08的Datasheet PDF文件第3页浏览型号74LS08的Datasheet PDF文件第4页浏览型号74LS08的Datasheet PDF文件第5页 
August 1986  
Revised March 2000  
DM74LS08  
Quad 2-Input AND Gates  
General Description  
This device contains four independent gates each of which  
performs the logic AND function.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS08M  
DM74LS08SJ  
DM74LS08N  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = AB  
Inputs  
Output  
A
L
B
L
Y
L
L
H
L
L
H
H
L
H
H
H = HIGH Logic Level  
L = LOW Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS006347  
www.fairchildsemi.com  

与74LS08相关器件

型号 品牌 描述 获取价格 数据表
74LS08A NXP AND Gate, LS Series, 4-Func, 2-Input, TTL, PDIP14

获取价格

74LS08F NXP IC LS SERIES, QUAD 2-INPUT AND GATE, CDIP14, Gate

获取价格

74LS08FC FAIRCHILD AND Gate, TTL, CDFP14,

获取价格

74LS08FCQM FAIRCHILD AND Gate, TTL, CDFP14,

获取价格

74LS08N NXP IC LS SERIES, QUAD 2-INPUT AND GATE, PDIP14, PLASTIC, DIP-14, Gate

获取价格

74LS08NA+1 RAYTHEON AND Gate, TTL, PDIP14,

获取价格