Dual 5 A, 20 V Synchronous Step-Down
Regulator with Integrated High-Side MOSFET
Data Sheet
ADP2325
FEATURES
TYPICAL APPLICATION CIRCUIT
Input voltage: 4.5 V to 20 V
1% output accuracy
V
R
IN
TOP1
C
C
IN1
C1
Integrated 48 mΩ typical high-side MOSFET
Flexible output configuration
Dual output: 5 A/5 A
C
SS1
R
BOT1
R
C1
C
BST1
L1
INTVCC
MODE
C
V
OUT1
INT
Parallel single output: 10 A
SW1
SCFG
TRK2
TRK1
Programmable switching frequency: 250 kHz to 1.2 MHz
External synchronization input with programmable phase
shift or internal clock output
M1
M2
C
OUT1
DL1
PGND
DL2
VDRV
C
DRV
ADP2325
GND
Selectable PWM or PFM mode operation
Adjustable current limit for small inductors
External compensation and soft start
Startup into precharged output
C
OUT2
L2
PGOOD2
V
OUT2
PGOOD1
SYNC
RT
SW2
C
BST2
Supported by ADIsimPowerTM design tool
R
OSC
R
C2
R
BOT2
V
APPLICATIONS
IN
C
C
C
IN2
C2
SS2
Communications infrastructure
Networking and servers
R
TOP2
Industrial and instrumentation
Healthcare and medical
Figure 1.
Intermediate power rail conversion
GENERAL DESCRIPTION
The ADP2325 is a full featured, dual output, step-down dc-to-dc
regulator based on a current mode architecture. The ADP2325
integrates two high-side power MOSFETs and two low-side drivers
for the external N-channel MOSFETs. The two pulse-width mod-
ulation (PWM) channels can be configured to deliver dual 5 A
outputs or a parallel-to-single 10 A output. The regulator operates
from input voltages of 4.5 V to 20 V, and the output voltage can
be as low as 0.6 V.
Independent enable inputs and power-good outputs provide
reliable power sequencing. To enhance system reliability, the device
includes undervoltage lockout (UVLO), overvoltage protection
(OVP), overcurrent protection, and thermal shutdown.
The ADP2325 operates over the −40°C to +125°C junction
temperature range and is available in a 32-lead LFCSP_WQ
package.
100
V
V
= 5.0V
= 3.3V
OUT
OUT
The switching frequency can be programmed from 250 kHz to
1.2 MHz, or it can be synchronized to an external clock to
minimize interference in multirail applications. The dual PWM
channels run 180° out of phase, thereby reducing input current
ripple as well as reducing the size of the input capacitor.
95
90
85
80
75
70
65
60
55
50
The bidirectional synchronization pin can be programmed at
a 60°, 90°, or 120° phase shift to provide for a stackable, multi-
phase power solution.
The ADP2325 can be configured to operate in pulse frequency
modulation (PFM) mode at a light load for higher efficiency or
in forced PWM mode for noise sensitive applications. External
compensation and soft start provide design flexibility.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT CURRENT (A)
Figure 2. Efficiency vs. Output Current at VIN = 12 V, fSW = 600 kHz
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
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