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7446APCQM PDF预览

7446APCQM

更新时间: 2024-11-18 13:00:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 解码器驱动器
页数 文件大小 规格书
6页 55K
描述
Decoder/Driver, TTL, PDIP16,

7446APCQM 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:compliant风险等级:5.85
Is Samacsys:NJESD-30 代码:R-PDIP-T16
JESD-609代码:e0逻辑集成电路类型:OTHER DECODER/DRIVER
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:5 V认证状态:Not Qualified
子类别:Decoder/Drivers标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

7446APCQM 数据手册

 浏览型号7446APCQM的Datasheet PDF文件第2页浏览型号7446APCQM的Datasheet PDF文件第3页浏览型号7446APCQM的Datasheet PDF文件第4页浏览型号7446APCQM的Datasheet PDF文件第5页浏览型号7446APCQM的Datasheet PDF文件第6页 
September 1986  
Revised February 2000  
DM7446A, DM7447A  
BCD to 7-Segment Decoders/Drivers  
General Description  
Features  
The DM7446A and DM7447A feature active-LOW outputs  
designed for driving common-anode LEDs or incandescent  
indicators directly. All of the circuits have full ripple-blank-  
ing input/output controls and a lamp test input. Segment  
identification and resultant displays are shown on a follow-  
ing page. Display patterns for BCD input counts above nine  
are unique symbols to authenticate input conditions.  
All circuit types feature lamp intensity modulation capa-  
bility  
Open-collector outputs drive indicators directly  
Lamp-test provision  
Leading/trailing zero suppression  
All of the circuits incorporate automatic leading and/or trail-  
ing-edge, zero-blanking control (RBI and RBO). Lamp test  
(LT) of these devices may be performed at any time when  
the BI/RBO node is at a HIGH logic level. All types contain  
an overriding blanking input (BI) which can be used to con-  
trol the lamp intensity (by pulsing) or to inhibit the outputs.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM7446AN  
DM7446AN  
N16E  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Connection Diagram  
© 2000 Fairchild Semiconductor Corporation  
DS006518  
www.fairchildsemi.com  

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