Datasheet > 74244

74244

更新时间： 2024-09-16 22:22:07

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		驱动器
页数	文件大小	规格书
6页	69K
描述
Octal 3-STATE Buffer/Line Driver/Line Receiver

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数据手册

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74244 数据手册

August 1986

Revised March 2000

DM74LS244

Octal 3-STATE Buffer/Line Driver/Line Receiver

General Description

Features

These buffers/line drivers are designed to improve both the

performance and PC board density of 3-STATE buffers/

drivers employed as memory-address drivers, clock driv-

ers, and bus-oriented transmitters/receivers. Featuring 400

mV of hysteresis at each low current PNP data line input,

they provide improved noise rejection and high fanout out-

puts and can be used to drive terminated lines down to

133Ω.

■ 3-STATE outputs drive bus lines directly

■ PNP inputs reduce DC loading on bus lines

■ Hysteresis at data inputs improves noise margins

■ Typical I_OL(sink current)

24 mA

■ Typical I_OH(source current) −15 mA

■ Typical propagation delay times

Inverting

10.5 ns

12 ns

Noninverting

■ Typical enable/disable time

18 ns

■ Typical power dissipation (enabled)

Inverting

130 mW

135 mW

Noninverting

Ordering Code:

Order Number Package Number

Package Description

DM74LS244WM

DM74LS244SJ

DM74LS244N

M20B

M20D

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Output

L = LOW Logic Level

H = HIGH Logic Level

X = Either LOW or HIGH Logic Level

Z = High Impedance

DS008442

www.fairchildsemi.com

12 3 4 5 6

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