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73S1215F-44IMR/F PDF预览

73S1215F-44IMR/F

更新时间： 2024-02-21 10:09:04
品牌 Logo 应用领域
TERIDIAN 多功能外围设备微控制器和处理器时钟
页数 文件大小 规格书
136页 1028K
描述
80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More

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73S1215F-44IMR/F 技术参数

生命周期：Transferred包装说明：LEAD FREE, QFN-44
Reach Compliance Code：unknown风险等级：5.74
Is Samacsys：N其他特性：OPERATES BETWEEN 3 TO 3.6 V WHEN USB IS USED
地址总线宽度：边界扫描：NO
总线兼容性：I2C; USB最大时钟频率：12 MHz
外部数据总线宽度：JESD-30 代码：S-XQCC-N44
长度：7 mm端子数量：44
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
认证状态：Not QualifiedRAM（字数）：2000
座面最大高度：0.85 mm最大供电电压：3.6 V
最小供电电压：2.7 V标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
宽度：7 mmBase Number Matches：1

73S1215F-44IMR/F 数据手册

 浏览型号73S1215F-44IMR/F的Datasheet PDF文件第130页浏览型号73S1215F-44IMR/F的Datasheet PDF文件第131页浏览型号73S1215F-44IMR/F的Datasheet PDF文件第132页浏览型号73S1215F-44IMR/F的Datasheet PDF文件第133页浏览型号73S1215F-44IMR/F的Datasheet PDF文件第134页浏览型号73S1215F-44IMR/F的Datasheet PDF文件第136页 
DS_1215F_003  
73S1215F Data Sheet  
1.4  
12/16/2008  
In Table 1, added more description to the VCC, VPC, VDD, SCL, SDA,  
PRES, SEC and TEST pins.  
In Section 1.3.2, changed “FLSH_ERASE” to “ERASE” and  
“FLSH_PGADR” to “PGADDR”. Added “The PGADDR register denotes  
the page address for page erase. The page size is 512 (200h) bytes and  
there are 128 pages within the flash memory. The PGADDR denotes the  
upper seven bits of the flash memory address such that bit 7:1 of the  
PGADDR corresponds to bit 15:9 of the flash memory address. Bit 0 of  
the PGADDR is not used and is ignored.” In the description of the  
PGADDR register, added “Note: the page address is shifted left by one bit  
(see detailed description above).”  
Changed the register address for ATRMsB from FE21 to FE1F.  
In Table 5, changed “FLSHCRL” to “FLSHCTL”.  
In Table 5, moved the TRIMPCtl bit description to FUSECtl and moved the  
FUSECtl bit description to TRIMPCtl.  
In Table 6, changed “PGADR” to “PGADDR”.  
In Table 7, added PGADDR.  
In Table 8, changed the reset value for RTCCtl from “0x81” to “0x00”.  
Added the RTCTrim0 and ACOMP registers. Deleted the OMP, VRCtl,  
LEDCal and LOCKCtl registers.  
In Table 23, corrected the descriptions for TCON.2 and TCON.0.  
In Table 62, added “Write data controls output level of pin LEDn. Read will  
report level of pin LEDn.” to the description of LEDD3, LEDD2 and  
LEDD1.  
In Section 1.7.15.5 (number 3), deleted “If CLKOFF/SCLKOFF is high and  
SYCKST is set=1(STXCtl, b7=1), Rlen=max will stop the clock at the  
selected (CLKLVL or SCLKLVL) level.”  
In Section 1.7.15.5, added “Synchronous card operation is broken down  
into three primary types. These are commonly referred to as 2-wire,  
3-wire and I2C synchronous cards. Each card type requires different  
control and timing and therefore requires different algorithms to access.  
Teridian has created an application note to provide detailed algorithms for  
each card type. Refer to the application note titled 73S12xxF  
Synchronous Card Design Application Note.”  
In the VccVtl.0 bit description, deleted “When in power down mode, VDD  
0V. VDD can only be turned on by pressing the ON/OFF switch or by  
=
application of 5V to VBUS. If VBUS power is available and SCPWRDN bit is  
set, it has no effect until VBUS is removed and VDD will shut off.”  
In Table 86 and Table 117, changed the SYCKST bit to I2CMODE.  
In Figure 26, replaced the schematic with a new schematic.  
Added Section 6, Ordering Information.  
Added Section 7, Related Documentation.  
Added Section 8, Contact Information.  
Formatted the document per new standard. Added section numbering.  
Rev. 1.4  
135  
1...132133134135136

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