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73M1903C-IMR/F

更新时间： 2024-02-28 12:10:48

品牌	Logo	应用领域
TERIDIAN		调制解调器消费电路商用集成电路
页数	文件大小	规格书
46页	452K
描述
Modem Analog Front End

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技术参数
数据手册

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73M1903C-IMR/F 技术参数

生命周期：	Transferred	包装说明：	ROHS COMPLIANT, MO-153AC, TSSOP-20
Reach Compliance Code：	unknown	风险等级：	5.59
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	R-PDSO-G20
长度：	6.5 mm	功能数量：	1
端子数量：	20	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	认证状态：	Not Qualified
座面最大高度：	1.1 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
宽度：	4.4 mm	Base Number Matches：	1

73M1903C-IMR/F 数据手册

73M1903C

Modem Analog Front End

DATA SHEET

SLAVE MODE AND DAISY CHAIN

If the SCLK pin is externally pulled down to ground by a <4.7KΩ resistor, the 79M1903C device is in the

slave mode, after reset. In this mode of operation the serial clock (SCLK) and FS are inputs to 79M1903C

provided by the Master device. The serial clock input must be connected to OSCIN pin while SCLK pin of

73M1903C is unconnected, except for the resistor connected to ground (see Figures 4 and 5). The

73M1903C PLL must be programmed to multiply the serial clock frequency by an appropriate factor in

order to obtain Fsys. Therefore the serial clock has to be continuous and without low frequency jitter (the

high frequency jitter is rejected by the 79M1903C PLL). The SckMode pin is not used since the Master

device provides FS and serial clock.

73M1903C

MCLK

(Master)

OSCIN

SCLK

OSCIN

(Slave)

SDOUT

SDIN

SDOUT

SDIN

SDOUT

HOST

(Master)

(Slave)

"x"

"1/0"

SckMode

TYPE

SCLK

TYPE

SCLK

"x" : don't care

73M1903C Master Mode

73M1903C Slave Mode

Figure 4: 73M1903C Host connection in master and slave mode

73M1903C

MCLK

SCLK

SDOUT

SDIN

OSCIN (Master)

OSCIN (Slave)

SDOUT

SDIN

SDOUT

SDIN

SDOUT

HOST

"x"

(Slave)

(Master)

SckMode

"1/0"

SckMode

SCLK

FSBD

TYPE

SCLK

TYPE

FSBD

73M1903C

OSCIN

(Slave)

OSCIN

(Slave)

"x" : don't care

SDIN

SDOUT

"x"

SckMode

SCLK

TYPE

SCLK

TYPE

Daisy chain for Slave mode

Figure 5: 73M1903C Daisy chaining for master/slave mode and slave modes

Daisy chain for Master/Slave mode

In order to daisy chain two or more 73M1903C devices, the master must be programmed into hardware

controlled control frame mode by setting the HC bit (bit 0 in Register01) to “1”, then set FSDEn (bit 3 in

Register06), and then set CkoutEn bit (bit 3 in Register01) to allow the FSD to come through. The first

Page: 9 of 46

Rev 4.3

1...6 7 8910 11 12...46

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73M1903-IM/F	TERIDIAN	Modem Analog Front End	获取价格