73K321L

更新时间： 2024-02-11 17:28:46

品牌	Logo	应用领域
东电化 - TDK		调制解调器
页数	文件大小	规格书
24页	134K
描述
CCITT V.23, V.21 Single-Chip Modem

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技术参数
数据手册

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73K321L 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.09	其他特性：	HALF DUPLEX; FULL DUPLEX
数据速率：	1.2 Mbps	JESD-30 代码：	R-PDIP-T22
功能数量：	1	端子数量：	22
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	Not Qualified
最大压摆率：	12 mA	标称供电电压：	5 V
表面贴装：	NO	电信集成电路类型：	MODEM
温度等级：	INDUSTRIAL	端子形式：	THROUGH-HOLE
端子位置：	DUAL	Base Number Matches：	1

73K321L 数据手册

73K321L

CCITT V.23, V.21

Single-Chip

PARALLEL MICROPROCESSOR CONTROL INTERFACE (continued)

NAME

TYPE

DESCRIPTION

PLCC/DIP

PIN NUMBER

Write. A low on this informs the 73K321L that data is available on

AD0-AD7 for writing into an internal register. Data is latched on the

rising edge of WR. No data is written unless both WR and the latched

CS are low.

SERIAL MICROPROCESSOR CONTROL INTERFACE

AD0-AD2

4-6

should be valid during any read or write operation.

DATA (AD7)

I/O

Serial Control Data. Data for a read/write operation is clocked in or

out on the falling edge of the EXCLK pin. The direction of data flow is

controlled by the RD pin. RD low outputs data. RD high inputs data.

Read. A low on this input informs the 73K321L that data or status

information is being read by the processor. The falling edge of the

RD signal will initiate a read from the addressed register. The RD

signal must continue for eight falling edges of EXCLK in order to read

all eight bits of the referenced register. Read data is provided LSB

first. Data will not be output unless the RD signal is active.

Write. A low on this input informs the 73K321L that data or status

information has been shifted in through the DATA pin and is available

for writing to an internal register. The normal procedure for a write is

to shift in data LSB first on the DATA pin for eight consecutive falling

edges of EXCLK and then to pulse WR low. Data is written on the

rising edge of WR.

NOTE: The Serial Control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes

DATA and AD0, AD1 and AD2 become the address only. See the Serial Control Timing diagrams on

page 18

1 2 345 6 7...24

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与73K321L相关器件

型号	品牌	描述	获取价格	数据表
73K321L-IH	TDK	CCITT V.23, V.21 Single-Chip Modem	获取价格
73K321L-IP	TDK	CCITT V.23, V.21 Single-Chip Modem	获取价格
73K321L-IP	TI	1.2kbps DATA, MODEM, PDIP28, 0.600 INCH, PLASTIC, DIP-28	获取价格
73K321SL-IP	TI	1.2kbps DATA, MODEM, PDIP22, 0.400 INCH, PLASTIC, DIP-22	获取价格
73K322L	TDK	CCITT V.23, V.22, V.21 Single-Chip Modem	获取价格
73K322L-IH	TDK	CCITT V.23, V.22, V.21 Single-Chip Modem	获取价格