73K224L-IP

更新时间： 2024-02-14 12:01:26

品牌	Logo	应用领域
东电化 - TDK		调制解调器电信集成电路光电二极管
页数	文件大小	规格书
32页	208K
描述
V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem

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技术参数
数据手册

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73K224L-IP 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	22
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.04	其他特性：	FULL DUPLEX
数据速率：	2.4 Mbps	JESD-30 代码：	R-PDIP-T22
长度：	27.686 mm	功能数量：	1
端子数量：	22	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	Not Qualified
座面最大高度：	5.08 mm	标称供电电压：	5 V
表面贴装：	NO	电信集成电路类型：	MODEM
温度等级：	INDUSTRIAL	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	10.16 mm	Base Number Matches：	1

73K224L-IP 数据手册

73K224L

V.22bis/V.22/V.21/Bell 212A/Bell 103

Single-Chip Modem

PIN DESCRIPTION

POWER

NAME

GND

VDD

TYPE DESCRIPTION

System Ground.

Power supply input, 5V -5% +10%. Bypass with 0.22 µF and 22 µF capacitors to

GND.

VREF

ISET

An internally generated reference voltage. Bypass with 0.22 µF capacitor to

GND.

Chip current reference. Sets bias current for op-amps. The chip current is set by

connecting this pin to VDD through a 2 MW resistor. Iset should be bypassed to

GND with a 0.22 µF capacitor.

PARALLEL MICROPROCESSOR INTERFACE

ALE

Address latch enable. The falling edge of ALE latches the address on AD0-AD2

and the chip select on CS.

AD0- AD7

I/O

Address/data bus. These bidirectional tri-state multiplexed lines carry infor-

mation to and from the internal registers.

/Tristate

Chip select. A low on this pin allows a read cycle or a write cycle to occur. AD0-

AD7 will not be driven and no registers will be written if CS (latched) is not active.

CS is latched on the falling edge of ALE.

CLK

Output clock. This pin is selectable under processor control to be either the

crystal frequency (for use as a processor clock) or 16 x the data rate for use as a

baud rate clock in QAM/DPSK modes only. The pin defaults to the crystal

frequency on reset.

INT

Interrupt. This open drain /weak pull-up, output signal is used to inform the

processor that a detect flag has occurred. The processor must then read the

detect register to determine which detect triggered the interrupt. INT will stay

active until the processor reads the detect register or does a full reset.

Read. A low requests a read of the 73K224L internal registers. Data cannot be

output unless both RD and the latched CS are active or low.

RESET

Reset. An active high signal on this pin will put the chip into an inactive state. All

control register bits (CR0, CR1, CR2, CR3, Tone) will be reset. The output of the

CLK pin will be set to the crystal frequency. An internal pull down resistor permits

power on reset using a capacitor to VDD.

Write. A low on this informs the 73K224L that data is available on AD0-AD7 for

writing into an internal register. Data is latched on the rising edge of WR. No data

is written unless both WR and the latched CS are active (low).

NOTE: The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes

DATA and AD0, AD1 and AD2 become the address only.

1 2 345 6 7...32

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