73K224L-IH

更新时间： 2024-01-15 20:46:15

品牌	Logo	应用领域
东电化 - TDK		调制解调器电信集成电路
页数	文件大小	规格书
32页	208K
描述
V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem

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技术参数
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73K224L-IH 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	22
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.04	其他特性：	FULL DUPLEX
数据速率：	2.4 Mbps	JESD-30 代码：	R-PDIP-T22
长度：	27.686 mm	功能数量：	1
端子数量：	22	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	Not Qualified
座面最大高度：	5.08 mm	标称供电电压：	5 V
表面贴装：	NO	电信集成电路类型：	MODEM
温度等级：	INDUSTRIAL	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	10.16 mm	Base Number Matches：	1

73K224L-IH 数据手册

73K224L

V.22bis/V.22/V.21/Bell 212A/Bell 103

Single-Chip Modem

DTE USER INTERFACE

NAME

TYPE DESCRIPTION

EXCLK

External Clock. This signal is used in synchronous transmission when the

external timing option has been selected. In the external timing mode the rising

edge of EXCLK is used to strobe synchronous transmit data available on the

TXD pin. Also used for serial control interface.

RXCLK

Tristate

Receive Clock. Tri stateable. The falling edge of this clock output is coincident

with the transitions in the serial received data output. The rising edge of RXCLK

can be used to latch QAM or DPSK valid output data. RXCLK will be active as

long as a carrier is present.

RXD

Weak

Received Digital Data Output. Serial receive data is available on this pin. The

data is always valid on the rising edge of RXCLK when in synchronous mode.

Pull-up RXD will output constant marks if no carrier is detected.

TXCLK

Tristate

Transmit Clock. Tri stateable. This signal is used in synchronous transmission to

latch serial input data on the TXD pin. Data must be provided so that valid data is

available on the rising edge of the TXCLK. The transmit clock is derived from

different sources depending upon the synchronization mode selection. In Internal

Mode the clock is generated internally. In External Mode TXCLK is phase locked

to the EXCLK pin. In Slave Mode TXCLK is phase locked to the RXCLK pin.

TXCLK is always active.

TXD

Transmit Digital Data Input. Serial data for transmission is input on this pin. In

synchronous modes, the data must be valid on the rising edge of the TXCLK

clock. In asynchronous modes (2400/1200/600 bit/s or 300 baud) no clocking is

necessary. DPSK data must be +1%, -2.5% or +2.3%, -2.5 % in extended

overspeed mode.

ANALOG INTERFACE AND OSCILLATOR

RXA

Received modulated analog signal input from the phone line.

Transmit analog output to the phone line.

TXA

XTL1

XTL2

These pins are for the internal crystal oscillator requiring a 11.0592 MHz parallel

mode crystal. Two capacitors from these pins to ground are also required for

proper crystal operation. Consult crystal manufacturer for proper values. XTL2

can also be driven from an external clock.

I/O

1 2 3 456 7 8...32

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与73K224L-IH相关器件

型号	品牌	描述	获取价格	数据表
73K224L-IP	TDK	V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem	获取价格
73K224L-IP	SST	Modem, 2.4kbps Data, PDIP28	获取价格
73K224LS-IP	SST	2.4kbps DATA, MODEM, PDIP22, 0.400 INCH, PLASTIC, DIP-22	获取价格
73K22IAL-IH	TDK	Modem, 1.2kbps Data, CMOS, PQCC28, PLASTIC, LCC-28	获取价格
73K22IAL-IP	TDK	Modem, 1.2kbps Data, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28	获取价格
73K302L	TDK	Single-Chip Modem	获取价格

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