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72V3672L10PFG8 PDF预览

72V3672L10PFG8

更新时间: 2024-10-01 01:22:43
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
29页 206K
描述
3.3 VOLT CMOS SyncBiFIFOTM

72V3672L10PFG8 数据手册

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3.3 VOLT CMOS SyncBiFIFOTM  
8,192 x 36 x 2  
IDT72V3672  
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags  
functions) or First Word Fall Through timing (using ORA, ORB, IRA  
and IRB flag functions)  
Available in space-saving 120-pin Thin Quad Flatpack (TQFP)  
Pin and functionally compatible versions of the 5V operating  
IDT23672  
Pin compatible to the lower density parts, IDT72V3642  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
FEATURES  
Memory storage capacity:  
IDT72V3672  
Supports clock frequencies up to 100MHz  
Fast access times of 6.5ns  
Free-running CLKA and CLKB may be asynchronous or coincident  
(simultaneous reading and writing of data on a single clock edge  
is permitted)  
Two independent clocked FIFOs buffering data in opposite direc-  
tions  
8,192 x 36 x 2  
DESCRIPTION  
Mailbox bypass register for each FIFO  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor Interface Control Logic  
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA  
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB  
The IDT72V3672 is a pin and functionally compatible version of the  
IDT723672, designed to run off a 3.3V supply for exceptionally low-power  
consumption. Thesedevicesaremonolithic,high-speed,low-power,CMOS  
BidirectionalSyncFIFO(clocked)memorieswhichsupportclockfrequencies  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
Port-A  
Control  
Logic  
W/RA  
ENA  
RAM  
ARRAY  
8,192 x 36  
MBA  
36  
FIFO1,  
Mail1  
Reset  
Logic  
RST1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO 1  
FS0  
FS1  
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
A0 - A35  
13  
B0 - B35  
FIFO 2  
Status Flag  
EFA/ORA  
FFB/IRB  
AFB  
Logic  
AEA  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
RST2  
RAM  
ARRAY  
CLKB  
CSB  
8,192 x 36  
Port-B  
Control  
Logic  
W/RB  
ENB  
Mail 2  
Register  
MBB  
4660 drw01  
MBF2  
CIDTOandMtheMIDTElogRoaCrereIgAisteLredtrTadeEmaMrkoPfInEtegRrateAdDTevUiceTRecEhnologRy,IAnc.NSynGcBEiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
APRIL 2017  
1
2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4660/6  
©

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