Datasheet > 72V261LA15TFGI8

72V261LA15TFGI8

更新时间： 2024-12-02 00:47:47

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
27页	361K
描述
3.3 VOLT CMOS SuperSync FIFO

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数据手册

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72V261LA15TFGI8 数据手册

3.3 VOLT CMOS SuperSync FIFO™

16,384 x 9

32,768 x 9

IDT72V261LA

IDT72V271LA

FEATURES:

• Program partial flags by either serial or parallel means

• Choose among the following memory organizations:

• Select IDT Standard timing (using EF and FF flags) or First

Word Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• Independent Read and Write clocks (permit reading and writing

simultaneously)

IDT72V261LA

IDT72V271LA

—

16,384 x 9

32,768 x 9

• Pin-compatible with the IDT72V281/72V291 and IDT72V2101/

72V2111SuperSync FIFOs

• Functionally compatible with the 5 Volt IDT72261/72271 family

• 10ns read/write cycle time (6.5ns access time)

• Fixed, low first word data latency time

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-

pin Slim Thin Quad Flat Pack (STQFP)

• 5V input tolerant

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information

• Partial Reset clears data, but retains programmable settings

• Retransmit operation with fixed, low first word data

latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag

can default to one of two preselected offsets

DESCRIPTION:

The IDT72V261LA/72V271LA are functionally compatible versions of

the IDT72261/72271 designed to run off a 3.3V supply for very low power

consumption. The IDT72V261LA/72V271LA are exceptionally deep, high

speed, CMOS First-In-First-Out (FIFO) memories with clocked read and

FUNCTIONAL BLOCK DIAGRAM

D0 -D8

WEN

WCLK

SEN

OFFSET REGISTER

INPUT REGISTER

FF/IR

PAF

EF/OR

PAE

FLAG

LOGIC

WRITE CONTROL

LOGIC

FWFT/SI

RAM ARRAY

16,384 x 9

32,768 x 9

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

Q0 -Q8

4673 drw 01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncisatrademarkofIntegratedDeviceTechnology, Inc.

JULY 2014

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-4673/5

12 3 4 5 6 7...27

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与72V261LA15TFGI8相关器件

型号	品牌	获取价格	描述	数据表
72V261LA15TFI	IDT	获取价格	TQFP-64, Tray
72V261LA15TFI9	IDT	获取价格	FIFO, 16KX9, 10ns, Synchronous, CMOS, PQFP64, STQFP-64
72V261LA20PF	IDT	获取价格	TQFP-64, Tray
72V261LA20PFG	IDT	获取价格	FIFO, 16KX9, 12ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64
72V261LA20PFG8	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V261LA20PFGI	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V261LA20PFGI8	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V261LA20TF8	IDT	获取价格	TQFP-64, Reel
72V261LA20TFG	IDT	获取价格	FIFO, 16KX9, 12ns, Synchronous, CMOS, PQFP64, SLIM, GREEN, TQFP-64
72V261LA20TFG8	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO

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