Datasheet > 72T3695L6-7BB

72T3695L6-7BB

更新时间： 2025-09-22 19:15:15

品牌	Logo	应用领域
瑞萨 - RENESAS		存储
页数	文件大小	规格书
57页	440K
描述
存储容量(Mb):1.125M（32K x 36）;内存数据长度(bit):32K ;字编码数(k):32K ;元器件封装:208-PBGA（17x17）;

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中文翻译

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数据手册

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72T3695L6-7BB 数据手册

2.5 VOLT HIGH-SPEED TeraSync^TMFIFO 36-BIT CONFIGURATIONS

IDT72T36105

IDT72T36115

IDT72T36125

65,536 x 36

131,072 x 36

262,144 x 36

FEATURES:

• User selectable input and output port bus-sizing

• Choose among the following memory organizations:

- x36 in to x36 out

- x36 in to x18 out

- x36 in to x9 out

- x18 in to x36 out

- x9 in to x36 out

• Big-Endian/Little-Endian user selectable byte representation

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable settings

• Empty, Full and Half-Full flags signal FIFO status

• Select IDT Standard timing (using EF and FF flags) or First Word

Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• JTAG port, provided for Boundary Scan function

• Available in 240-pin (19mm x 19mm) Plastic Ball Grid Array (PBGA)

• Easily expandable in depth and width

IDT72T36105

IDT72T36115

IDT72T36125

⎯

65,536 x 36

131,072 x 36

262,144 x 36

• Up to 225 MHz Operation of Clocks

• User selectable HSTL/LVTTL Input and/or Output

• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage

• 3.3V Input tolerant

• Read Enable & Read Clock Echo outputs aid high speed operation

• User selectable Asynchronous read and/or write port timing

• Mark & Retransmit, resets read pointer to user marked position

• Write Chip Select (WCS) input enables/disables Write operations

• Read Chip Select (RCS) synchronous to RCLK

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets

• Independent Read and Write Clocks (permit reading and writing

simultaneously)

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

• Green parts are available, see ordering information

• Program programmable flags by either serial or parallel means

• Selectable synchronous/asynchronous timing modes for Almost-

Empty and Almost-Full flags

• Separate SCLK input for Serial programming of flag offsets

FUNCTIONALBLOCKDIAGRAM

D0 - Dn (x36, x18 or x9)

LD SEN

SCL K

WEN

WCL K / WR

WCS

INPUT REGISTER

OF F SET REGISTER

FF/IR

PAF

EF/OR

PAE

F WF T/SI

PF M

WRI TE CON TROL

LOGIC

ASYW

F LAG

LOGIC

RAM ARRAY

WRITE POINTER

65,536 x 36

131,072 x36

262,144 x 36

F SEL0

F SEL1

CONTROL

LOGIC

REA D P OI N TER

BUS

CONF IGURATION

REA D

CONTROL

LOGIC

MARK

ASYR

MRS

PRS

OUTPUT REGISTER

RESET

LOGIC

TCK

TRST

TMS

TDO

RCL K / RD

REN

JTAGCONTROL

(BOUNDARY SCAN)

RCS

TDI

Vr ef

WHSTL

RHSTL

SHSTL

HSTL I/0

CONTROL

EREN

5907 dr w01

Q0 - Qn (x36, x18 or x9)

ERCL K

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheTeraSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.

JUNE 2017

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-5907/21

12 3 4 5 6 7...57

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与72T3695L6-7BB相关器件

型号	品牌	获取价格	描述	数据表
72T3695L6-7BBG	IDT	获取价格	FIFO, 32KX36, 3.8ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, B
72T3695L6-7BBGI	IDT	获取价格	2.5 VOLT HIGH-SPEED TeraSync FIFO 36-BIT CONFIGURATIONS
72T40108L10BBG	IDT	获取价格	FIFO, 64KX40, 4.5ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, B
72T40108L4BB	IDT	获取价格	PBGA-208, Tray
72T40108L4BBG	IDT	获取价格	FIFO, 64KX40, 3.2ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, B
72T40108L5BB	IDT	获取价格	PBGA-208, Tray
72T40108L5BBG	IDT	获取价格	FIFO, 64KX40, 3.6ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, B
72T40108L6-7BB	IDT	获取价格	PBGA-208, Tray
72T40108L6-7BBG	IDT	获取价格	FIFO, 64KX40, 3.8ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, B
72T40108L6-7BBGI	IDT	获取价格	FIFO, 64KX40, 3.8ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, B

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