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72841L10PFG8 PDF预览

72841L10PFG8

更新时间: 2024-02-20 15:32:46
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
16页 344K
描述
DUAL CMOS SyncFIFO

72841L10PFG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TQFP
包装说明:LQFP, QFP64,.66SQ,32针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.21
最长访问时间:6.5 ns最大时钟频率 (fCLK):100 MHz
周期时间:10 nsJESD-30 代码:S-PQFP-G64
JESD-609代码:e3长度:14 mm
内存密度:36864 bit内存集成电路类型:OTHER FIFO
内存宽度:9湿度敏感等级:3
功能数量:1端子数量:64
字数:4096 words字数代码:4000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4KX9
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP64,.66SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.01 A
子类别:FIFOs最大压摆率:0.06 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

72841L10PFG8 数据手册

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IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM  
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9  
COMMERCIAL AND INDUSTRIAL  
TEMPERATURERANGES  
PIN DESCRIPTIONS  
TheIDT72801/72811/72821/72831/72841/72851stwoFIFOs, referred descriptiondefinestheinputandoutputsignalsforFIFOA.Thecorrespond-  
to as FIFO A and FIFO B, are identical in every respect. The following ing signal names for FIFO B are provided in parentheses.  
Symbol  
DA0-DA8  
DB0-DB8  
RSA, RSB  
Name  
ADataInputs  
BDataInputs  
Reset  
I/O  
Description  
I
I
I
9-bit data inputs to RAM array A.  
9-bit data inputs to RAM array B.  
When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to  
the first location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go  
LOW. After power-up, a reset of both FIFOs A and B is required before an initial Write.  
WCLKA  
WCLKB  
WriteClock  
I
I
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write  
enable(s)areasserted.  
WENA1  
WENB1  
WriteEnable1  
If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only Write  
Enable pin that can be used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO  
on every LOW-to-HIGH transition WCLKA (WCLKB). If the FIFO is configured to have two write enables,  
WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into the FIFO. Data  
will not be written into the FIFO if FFA (FFB) is LOW.  
WENA2/LDA  
WENB2/LDB  
WriteEnable2/  
Load  
I
FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB)  
is HIGH at reset, this pin operates as a second write enable. If WENA2/LDA (WENB2/LDB) is LOW  
at reset this pin operates as a control to load and read the programmable flag offsets for its respective array.  
If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW  
and WENA2 (WENB2) must be HIGH to write data into FIFO A (B). Data will not be written into FIFO A (B)  
if FFA (FFB) is LOW. If the FIFO is configured to have programmable flags, LDA (LDB) is held LOW to write or  
readtheprogrammableflagoffsets.  
QA0-QA8  
QB0-QB8  
ADataOutputs  
BDataOutputs  
ReadClock  
O
O
I
9-bit data outputs from RAM array A.  
9-bit data outputs from RAM array B.  
RCLKA  
RCLKB  
Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1  
(RENB1) and RENA2 (RENB2) are asserted.  
RENA1  
RENB1  
Read Enable 1  
Read Enable 2  
OutputEnable  
EmptyFlag  
I
I
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every  
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.  
RENA2  
RENB2  
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every  
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW.  
OEA  
OEB  
I
When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the  
outputsDA0-DA8(DB0-DB8)willbeinahigh-impedancestate.  
EFA  
EFB  
O
O
When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited.  
When EFA (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).  
PAEA  
PAEB  
Programmable  
Almost-Empty  
Flag  
When PAEA (PAEB) is LOW, FIFO A (B) is almost-empty based on the offset programmed into the  
appropriateoffsetregister. ThedefaultoffsetatresetisEmpty+7. PAEA (PAEB)issynchronizedto  
RCLKA (RCLKB).  
PAFA  
PAFB  
Programmable  
Almost-FullFlag  
O
O
When PAFA (PAFB) is LOW, FIFO A (B) is almost-full based on the offset programmed into the appropriate  
offset register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB).  
FFA  
FFB  
VCC  
Full Flag  
When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited.  
When FFA (FFB) is HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).  
+5V power supply pin.  
Power  
GND  
Ground  
0V ground pin.  
MARCH 2013  
3

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