IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
accordingtotype,sendingonekindtoFIFOAandtheotherkindtoFIFOB.Then,
at theoutputs,eachdatatypeistransferredtoitsappropriatedestination.Additional
IDT72801/72811/72821/72831/72841/72851s permit more than two priority
levels.Prioritybufferingisparticularlyusefulinnetworkapplications.
TWO PRIORITY DATA BUFFER
CONFIGURATION
The two FIFOs contained in the IDT72801/72811/72821/72831/72841/
72851canbeusedtoprioritizetwodifferenttypesofdatasharedonasystembus.
When writing from the bus to the FIFO, control logic sorts the intermixed data
Image Processing
RAM ARRAY A
Card
Clock
RCLKA
WCLKA
OEA
Address
Control
WENA1
RENA
9
9
DA0-DA8
Q
A0-QA8
Data
I/O Data
RENA2
WENA2
VCC
Processor
Clock
IDT
72801
72811
72821
72831
72841
72851
Address
Control
Voice Processing
Card
Data
9
9
RAM ARRAY B
Clock
RCLKB
WCLKB
WENB1
OEB2
Address
Control
RAM
RENB1
I/O Data
D
B0-DB8
Data
Q
B0-QB8
9
9
RENB2
WENB2
3034 drw 17
VCC
Figure 16. Block Diagram of Two Priority Configuration
processor can write data to a peripheral controller via FIFO A, and, in turn,
the peripheral controller can write the processor via FIFO B.
BIDIRECTIONAL CONFIGURATION
The two FIFOs of the IDT72801/72811/72821/72831/72841/72851 can
be used to buffer data flow in two directions. In the example that follows, a
RAM ARRAY A
V
CC
RENA2
WENA2
RCLKA
WCLKA
OEA
WENA1
RENA1
9
Peripheral
Controller
DA0-DA8
QA0-QA8
Processor
Clock
9
IDT
DMA Clock
72801
72811
72821
72831
72841
72851
Address
Control
Address
Control
I/O Data
Data
Data
RAM ARRAY B
9
9
RCLKB
WENB1
RENB1
RAM
9
WCLKB
OEB
QB0-QB8
3034 drw 18
DB0-DB8
RENB2
9
9
WENB2
Figure 17. Block Diagram of Bidirectional Configuration
MARCH 2013
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