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72805LB15BGG PDF预览

72805LB15BGG

更新时间: 2024-11-29 00:47:55
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
26页 265K
描述
CMOS DUAL SyncFIFO

72805LB15BGG 数据手册

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CMOS DUAL SyncFIFO™  
DUAL 256 x 18  
DUAL 512 x 18  
DUAL 1,024 x 18  
DUAL 4,096 x 18  
IDT72805LB  
IDT72815LB  
IDT72825LB  
IDT72845LB  
Easily expandable in depth and width  
FEATURES:  
Asynchronous or coincident Read and Write clocks  
Asynchronous or synchronous programmable Almost-Empty  
and Almost-Full flags with default settings  
The IDT72805LB is equivalent to two IDT72205LB 256 x 18 FIFOs  
The IDT72815LB is equivalent to two IDT72215LB 512 x 18 FIFOs  
The IDT72825LB is equivalent to two IDT72225LB 1,024 x 18 FIFOs  
The IDT72845LB is equivalent to two IDT72245LB 4,096 x 18 FIFOs  
Offers optimal combination of large capacity (8K), high speed,  
design flexibility, and small footprint  
Half-Full flag capability  
Output Enable puts output data bus in high-impedance state  
High-performance submicron CMOS technology  
Available in the 128-pin Thin Quad Flatpack (TQFP). Also  
available for the IDT72805LB/72815LB/72825LB, in the 121-lead,  
16 x 16 mm plastic Ball Grid Array (PBGA)  
Ideal for the following applications:  
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-
-
-
-
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Network switching  
Two level prioritization of parallel data  
Bidirectional data transfer  
Bus-matching between 18-bit and 36-bit data paths  
Width expansion to 36-bit per package  
Depth expansion to 8,192 words per package  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
DESCRIPTION:  
10ns read/write cycle time, 6.5ns access time  
IDT Standard or First Word Fall Through timing  
Single or double register-buffered Empty and Full Flags  
The IDT72805LB/72815LB/72825LB/72845LB are dual 18-bit-wide syn-  
chronous (clocked) First-in, First-out (FIFO) memories. One dual IDT72805LB/  
FUNCTIONAL BLOCK DIAGRAM  
HF A/(WX OA )  
PAEA  
F F A/IR  
A
EF A/  
WCLKA  
ORA  
WCLKB  
WEN B  
DA0-DA17  
DB0-DB17  
WEN A  
LDA  
LDB  
PAFA  
INPUT  
OFFSET  
INPUT  
OFFSET  
REGISTER  
REGISTER  
REGISTER  
REGISTER  
F F B/IRB  
PAF B  
EF B/ORB  
PAEB  
HF B/(WX OB )  
FLAG  
WRITE  
FLAG  
LOGIC  
WRITE  
CONTROL  
LOGIC  
LOGIC  
RAM  
CONTROL  
LOGIC  
ARRAY  
RAM  
256 x 18  
512 x 18  
1,024 x 18  
4,096 x 18  
ARRAY  
256 x 18  
512 x 18  
1,024 x 18  
4,096 x 18  
READ  
POINTER  
WRITE  
READ  
POINTER  
WRITE  
POINTER  
POINTER  
READ  
CONTROL  
LOGIC  
F LA  
WX I A  
(HF A)/WX OA  
RX I A  
READ  
CONTROL  
LOGIC  
EXPANSION  
LOGIC  
EXPANSION  
LOGIC  
OUTPUT  
REGISTER  
OUTPUT  
RX OA  
REGISTER  
RESET  
LOGIC  
RESET  
LOGIC  
RSA  
RCLKB  
RSB  
RX OB  
RX I B  
(HF B)/WX OB  
WX I B  
F LB  
RCLKA  
OEB  
QA0-QA17  
REN B  
REN A  
OEA  
QB0-QB17  
3139 drw 01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MAY 2016  
©2016IntegratedDeviceTechnology,Inc.Allrightsreserved.Productspecificationssubjecttochangewithoutnotice.  
DSC-3139/9  

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