CMOS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36
4,096 x 36
8,192 x 36
IDT723653
IDT723663
IDT723673
• Big- or Little-Endian format for word and byte bus sizes
• Retransmit Capability
• Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
FEATURES
• Memory storage capacity:
IDT723653
IDT723663
IDT723673
–
–
–
2,048 x 36
4,096 x 36
8,192 x 36
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
• Clock frequencies up to 83 MHz (8 ns access time)
• Clocked FIFO buffering data from Port A to Port B
• IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
• Serial or parallel programming of partial flags
• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
• Easily expandable in width and depth
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
• Pin compatible with the lower density parts, IDT723623/723633/
723643
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
CSA
Port-A
W/RA
Control
ENA
Logic
MBA
36
RAM ARRAY
36
36
FIFO1
Mail1,
Mail2,
Reset
Logic
2,048 x 36
4,096 x 36
8,192 x 36
RS1
RS2
PRS
36
RT
RTM
FIFO
Retransmit
Logic
Write
Pointer
Read
Pointer
A0-A35
B0-B35
Status Flag
Logic
EF/OR
AE
FF/IR
AF
36
36
FS2
FS0/SD
FS1/SEN
Programmable Flag
Offset Registers
Timing
Mode
FWFT
13
CLKB
CSB
W/RB
ENB
MBB
BE
Port-B
Control
Logic
BM
SIZE
Mail 2
Register
5610 drw01
MBF2
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FEBRUARY 2009
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5610/6