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72291L15PFGI PDF预览

72291L15PFGI

更新时间: 2024-01-01 22:22:33
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
26页 418K
描述
FIFO, 128KX9, 10ns, Synchronous, CMOS, PQFP64

72291L15PFGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:QFP, QFP64,.63SQ,32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.44
最长访问时间:10 ns其他特性:RETRANSMIT; AUTO POWER DOWN
最大时钟频率 (fCLK):66.7 MHz周期时间:15 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
内存密度:1179648 bit内存集成电路类型:OTHER FIFO
内存宽度:9湿度敏感等级:3
功能数量:1端子数量:64
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX9
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP64,.63SQ,32
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
最大待机电流:0.02 A子类别:FIFOs
最大压摆率:0.08 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
Base Number Matches:1

72291L15PFGI 数据手册

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IDT72281/72291  
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,  
willshiftthewordfrominternalmemorytothedataoutputlines.  
DESCRIPTION(CONTINUED)  
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectlyto  
thedataoutputlinesafter threetransitionsoftheRCLKsignal.ARENdoesnot  
havetobeassertedforaccessingthefirstword.However,subsequentwords  
writtentotheFIFOdorequireaLOWonRENforaccess. ThestateoftheFWFT/  
SIinputduringMasterResetdeterminesthetimingmodeinuse.  
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFOcan  
provide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs  
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding  
data inputs of the next). No external logic is required.  
TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable  
(WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen  
WENisasserted.TheoutputportiscontrolledbyaReadClock(RCLK)input  
andReadEnable(REN)input. DataisreadfromtheFIFOoneveryrisingedge  
ofRCLKwhenRENisasserted. AnOutputEnable(OE)inputisprovidedfor  
three-statecontroloftheoutputs.  
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0  
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency  
oftheoneclockinputwithrespecttotheother.  
TheseFIFOshavefiveflagpins,EF/OR(EmptyFlagorOutputReady),FF/  
IR(FullFlagorInputReady),HF(Half-fullFlag),PAE(ProgrammableAlmost-  
Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFFfunctions  
areselectedinIDTStandardmode. TheIRandORfunctionsareselectedin  
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT  
Standard mode and First Word Fall Through (FWFT) mode.  
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear  
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread  
PINCONFIGURATIONS  
PIN 1  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
WEN  
SEN  
DC(1)  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
DNC(3)  
DNC(3)  
GND  
DNC(3)  
DNC(3)  
2
3
VCC  
4
VCC  
5
GND(2)  
GND(2)  
GND(2)  
GND(2)  
GND(2)  
GND(2)  
GND(2)  
GND(2)  
GND(2)  
D8  
6
VCC  
DNC(3)  
DNC(3)  
DNC(3)  
GND  
DNC(3)  
DNC(3)  
Q8  
7
8
9
10  
11  
12  
13  
14  
15  
16  
Q7  
Q6  
D7  
GND  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
4675 drw 02  
TQFP (PN64-1, ORDER CODE: PF)  
STQFP (PP64-1, ORDER CODE: TF)  
TOP VIEW  
NOTES:  
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.  
2. This pin may either be tied to GND or left open.  
3. DNC = Do Not Connect.  
2

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